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Several fixes and addition of 80486 instructions

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This commit is contained in:
ceriel 1992-09-16 16:10:30 +00:00
parent 94ec8e495e
commit be227c5f88
4 changed files with 48 additions and 7 deletions
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4
mach/i386/as/mach2.c
View file

@ -59,4 +59,8 @@
%token <y_word> FST_ST2
%token <y_word> ST
/* Intel 80486 tokens */
%token <y_word> EXTOPBW
%token <y_word> BSWAP
%type <y_valu> st_i
%type <y_valu> reg

28
mach/i386/as/mach3.c
View file

@ -51,6 +51,9 @@
0, RSYSDR, 3, "dr3",
0, RSYSDR, 6, "dr6",
0, RSYSDR, 7, "dr7",
0, RSYSTR, 3, "tr3", /* i486 */
0, RSYSTR, 4, "tr4", /* i486 */
0, RSYSTR, 5, "tr5", /* i486 */
0, RSYSTR, 6, "tr6",
0, RSYSTR, 7, "tr7",
0, ADDOP, 000, "addb",
@ -202,9 +205,9 @@
0, NOOP_1, 057, "das",
0, NOOP_1, 067, "aaa",
0, NOOP_1, 077, "aas",
0, NOOP_2, 017+06<<8, "clts",
0, NOOP_2, 0324+012<<8, "aam",
0, NOOP_2, 0325+012<<8, "aad",
0, NOOP_2, 017+(06<<8), "clts",
0, NOOP_2, 0324+(012<<8), "aam",
0, NOOP_2, 0325+(012<<8), "aad",
0, NOTOP, 020, "notb",
0, NOTOP, 021, "not",
0, NOTOP, 030, "negb",
@ -294,6 +297,7 @@
0, FNOOP, FESC+1+(0xE0<<8), "fchs",
0, FNOOP, FESC+3+(0xE2<<8), "fclex",
0, FNOOP, FESC+6+(0xD9<<8), "fcompp",
0, FNOOP, FESC+2+(0xE9<<8), "fucompp",
0, FNOOP, FESC+1+(0xF6<<8), "fdecstp",
0, FNOOP, FESC+3+(0xE1<<8), "fdisi",
0, FNOOP, FESC+3+(0xE0<<8), "feni",
@ -312,6 +316,7 @@
0, FNOOP, FESC+1+(0xFE<<8), "fsin",
0, FNOOP, FESC+1+(0xFB<<8), "fsincos",
0, FNOOP, FESC+1+(0xF8<<8), "fprem",
0, FNOOP, FESC+1+(0xF5<<8), "fprem1",
0, FNOOP, FESC+1+(0xF2<<8), "fptan",
0, FNOOP, FESC+1+(0xFC<<8), "frndint",
0, FNOOP, FESC+1+(0xFD<<8), "fscale",
@ -320,7 +325,7 @@
0, FNOOP, FESC+1+(0xE5<<8), "fxam",
0, FNOOP, FESC+1+(0xF4<<8), "fxtract",
0, FNOOP, FESC+1+(0xF1<<8), "fyl2x",
0, FNOOP, FESC+1+(0xF9<<8), "fyl2pi",
0, FNOOP, FESC+1+(0xF9<<8), "fyl2xp1",
0, FMEM, FESC+6+(0<<11), "fiadds",
0, FMEM, FESC+2+(0<<11), "fiaddl",
@ -382,10 +387,12 @@
0, FST_I, FESC+1+(0xC0<<8), "fld",
0, FST_I, FESC+5+(0xD0<<8), "fst",
0, FST_I, FESC+5+(0xC8<<8), "fstp",
0, FST_I, FESC+5+(0xD8<<8), "fstp",
0, FST_I, FESC+1+(0xC8<<8), "fxch",
0, FST_I, FESC+0+(0xD0<<8), "fcom",
0, FST_I, FESC+5+(0xE0<<8), "fucom",
0, FST_I, FESC+0+(0xD8<<8), "fcomp",
0, FST_I, FESC+5+(0xE8<<8), "fucomp",
0, FST_I, FESC+5+(0xC0<<8), "ffree",
0, FST_ST, FESC+0+(0xC0<<8), "fadd",
@ -400,3 +407,14 @@
0, FST_ST2, FESC+2+(0xE0<<8), "fsubp",
0, FST_ST2, FESC+0+(0xE8<<8), "fsubr",
0, FST_ST2, FESC+2+(0xE8<<8), "fsubrp",
/* Intel 486 instructions */
0, EXTOPBW, 0xC0, "xaddb",
0, EXTOPBW, 0xC1, "xadd",
0, EXTOPBW, 0xA6, "cmpxchgb",
0, EXTOPBW, 0xA7, "cmpxchg",
0, BSWAP, 0xC8, "bswap",
0, NOOP_2, 017+(010<<8), "invd",
0, EXTOP1, 071, "invlpg",
0, NOOP_2, 017+(011<<8), "wbinvd",

21
mach/i386/as/mach4.c
View file

@ -129,7 +129,7 @@ oper : NOOP_1
emit2((int)($2.val));
}
| SETCC ea_2
{ emit1(0xF); emit1($1); ea_2(0);}
{ emit1(0xF); emit1($1|0x90); ea_2(0);}
| XCHG ea_ea
{ xchg($1);}
| TEST ea_ea
@ -172,6 +172,8 @@ oper : NOOP_1
{ emit1($1); emit1($1>>8);}
| FMEM mem
{ emit1($1); ea_2(($1>>8)&070);}
| FMEM_AX mem
{ emit1($1); ea_2(($1>>8)&070);}
| FMEM_AX R32
{ if ($2 != 0) {
serror("illegal register");
@ -190,6 +192,13 @@ oper : NOOP_1
{ emit1($1|4); emit1((($1>>8)|$2)); }
| FST_ST2 st_i ',' ST
{ emit1($1|4); emit1((($1>>8)|$2)^010); }
/* 486 instructions */
| BSWAP R32
{ emit1(0xF); emit1($1|$2); }
| EXTOPBW reg ',' ea_2
{ regsize($1);
emit1(0xF); emit1($1); ea_2($2<<3);
}
;
st_i : ST '(' absexp ')'
@ -263,6 +272,16 @@ ea_2 : mem
RELOMOVE(rel_2, relonami);
}
;
reg : R8 { reg_1 = ($1 | IS_R8) | (address_long ? 0 : 0300);
rm_1 = 0;
$$ = $1;
}
| R32
{ reg_1 = ($1 | IS_R32) | (address_long ? 0 : 0310);
rm_1 = 0;
$$ = $1;
}
;
ea_1 : ea_2
{ op_1 = op_2;
RELOMOVE(rel_1, rel_2);

2
mach/i386/as/mach5.c
View file

@ -524,7 +524,7 @@ bittestop(opc)
emit1((int)(exp_2.val));
}
else if (is_reg(reg_2)) {
emit1(0203 | opc);
emit1(0203 | (opc<<3));
ea_1((reg_2&7)<<3);
}
else badsyntax();