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Some minor modifications reflecting some changes in the peephole optimizer

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This commit is contained in:
ceriel 1992-09-01 10:19:21 +00:00
parent 6f03cff48f
commit d18493b0ac
9 changed files with 162 additions and 190 deletions
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58
mach/i386/ncg/table
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@ -516,14 +516,8 @@ pat stl lol $1==$2
pat sdl ldl $1==$2 leaving dup 8 sdl $1 pat sdl ldl $1==$2 leaving dup 8 sdl $1
pat lol lol $1==$2
#ifdef REGVARS #ifdef REGVARS
&& inreg($1) <= 0 pat lol dup stl $2==4 && inreg($1) <= 0 && inreg($3) > 0
#endif
leaving lol $1 dup 4
#ifdef REGVARS
pat lol lol stl $1==$2 && inreg($1) <= 0 && inreg($3) > 0
kills regvar($3) kills regvar($3)
gen move {LOCAL,$1,4}, {LOCAL,$3,4} gen move {LOCAL,$1,4}, {LOCAL,$3,4}
yields {LOCAL,$3,4} yields {LOCAL,$3,4}
@ -535,10 +529,8 @@ pat ste loe $1==$2 leaving dup 4 ste $1
pat sde lde $1==$2 leaving dup 8 sde $1 pat sde lde $1==$2 leaving dup 8 sde $1
pat loe loe $1==$2 leaving loe $1 dup 4
#ifdef REGVARS #ifdef REGVARS
pat loe loe stl $1==$2 && inreg($3) > 0 pat loe dup stl $2==4 && inreg($3) > 0
kills regvar($3) kills regvar($3)
gen move {EXTERN,$1}, {LOCAL,$3,4} gen move {EXTERN,$1}, {LOCAL,$3,4}
yields {LOCAL,$3,4} yields {LOCAL,$3,4}
@ -550,9 +542,7 @@ pat lil inreg($1) > 0 yields {indir_r, regvar($1)}
pat lil pat lil
uses ADDREG={indir_r_off,ebp,$1} yields {indir_r,%a} uses ADDREG={indir_r_off,ebp,$1} yields {indir_r,%a}
pat lil lil $1==$2 leaving lil $1 dup 4 pat lil dup stl $2==4 leaving lil $1 stl $3 lol $3
pat lil lil stl $1==$2 leaving lil $1 stl $3 lol $3
pat sil lil $1==$2 leaving dup 4 sil $1 pat sil lil $1==$2 leaving dup 4 sil $1
@ -1806,42 +1796,42 @@ pat lol ngi stl $1==$3 && $2==4
kills indir, locals %ind+%size>$1 && %ind<$1+4 kills indir, locals %ind+%size>$1 && %ind<$1+4
gen neg {LOCAL, $1, 4} gen neg {LOCAL, $1, 4}
pat lol lol adp stl loi stl $1==$2 && $2==$4 && $5<=4 pat lol dup adp stl loi stl $1==$4 && $2==4 && $5<=4
leaving lol $1 loi $5 stl $6 lol $2 adp $3 stl $4 leaving lol $1 loi $5 stl $6 lol $1 adp $3 stl $4
#ifdef REGVARS #ifdef REGVARS
pat lol lol adp stl loi loc loc cii $1==$2 && $2==$4 && $5==1 && inreg($1) > 0 && $6==1 && $7==4 pat lol dup adp stl loi loc loc cii $1==$4 && $2==4 && $5==1 && inreg($1) > 0 && $6==1 && $7==4
uses REG uses REG
gen movsxb %a,{indir_r1, regvar($1)} gen movsxb %a,{indir_r1, regvar($1)}
yields %a yields %a
leaving lol $2 adp $3 stl $4 leaving lol $1 adp $3 stl $4
pat lol lol adp stl loi $1==$2 && $2==$4 && $5==1 && inreg($1) > 0 pat lol dup adp stl loi $1==$4 && $2==4 && $5==1 && inreg($1) > 0
uses REG1 = {indir_r1, regvar($1)} uses REG1 = {indir_r1, regvar($1)}
yields %a yields %a
leaving lol $2 adp $3 stl $4 leaving lol $1 adp $3 stl $4
pat lol lol adp stl loi loc loc cii $1==$2 && $2==$4 && $5==2 && inreg($1) > 0 && $6==2 && $7==4 pat lol dup adp stl loi loc loc cii $1==$4 && $2==4 && $5==2 && inreg($1) > 0 && $6==2 && $7==4
uses REG uses REG
gen movsx %a,{indir_r2, regvar($1)} gen movsx %a,{indir_r2, regvar($1)}
yields %a yields %a
leaving lol $2 adp $3 stl $4 leaving lol $1 adp $3 stl $4
pat lol lol adp stl loi $1==$2 && $2==$4 && $5==2 && inreg($1) > 0 pat lol dup adp stl loi $1==$4 && $2==4 && $5==2 && inreg($1) > 0
uses REG2 = {indir_r2, regvar($1)} uses REG2 = {indir_r2, regvar($1)}
yields %a yields %a
leaving lol $2 adp $3 stl $4 leaving lol $4 adp $3 stl $4
pat lol lol adp stl loi $1==$2 && $2==$4 && $5==4 && inreg($1) > 0 pat lol dup adp stl loi $1==$4 && $2==4 && $5==4 && inreg($1) > 0
uses REG = {indir_r, regvar($1)} uses REG = {indir_r, regvar($1)}
yields %a yields %a
leaving lol $2 adp $3 stl $4 leaving lol $4 adp $3 stl $4
pat adp stl inreg($2) > 0 leaving stl $2 lol $2 adp $1 stl $2 pat adp stl inreg($2) > 0 leaving stl $2 lol $2 adp $1 stl $2
#endif #endif
pat lol lol adp stl $1==$2 && $2==$4 pat lol dup adp stl $1==$4 && $2==4
uses ADDREG={LOCAL,$1,4} yields %a uses ADDREG={LOCAL,$1,4} yields %a
leaving lol $2 adp $3 stl $2 leaving lol $4 adp $3 stl $4
pat lol inl $1==$2 pat lol inl $1==$2
uses REG={LOCAL,$1,4} yields %a uses REG={LOCAL,$1,4} yields %a
@ -1866,20 +1856,20 @@ kills indir, locals %ind+%size>$1 && %ind<$1+4
gen not {LOCAL, $1, 4} gen not {LOCAL, $1, 4}
#ifdef REGVARS #ifdef REGVARS
pat lil lil adp sil $1==$2 && $1==$4 && inreg($1)==reg_any pat lil dup adp sil $1==$4 && $2==4 && inreg($1)==reg_any
uses ADDREG={indir_r, regvar($1)} uses ADDREG={indir_r, regvar($1)}
yields %a yields %a
leaving lil $1 adp $3 sil $4 leaving lil $4 adp $3 sil $4
pat lil lil inc sil $1==$2 && $1==$4 && inreg($1)==reg_any pat lil dup inc sil $1==$4 && $2==4 && inreg($1)==reg_any
uses REG={indir_r, regvar($1)} uses REG={indir_r, regvar($1)}
yields %a yields %a
leaving lil $1 inc sil $4 leaving lil $4 inc sil $4
pat lil lil dec sil $1==$2 && $1==$4 && inreg($1)==reg_any pat lil dup dec sil $1==$4 && $2==4 && inreg($1)==reg_any
uses REG={indir_r, regvar($1)} uses REG={indir_r, regvar($1)}
yields %a yields %a
leaving lil $1 dec sil $4 leaving lil $4 dec sil $4
#endif #endif
pat lil adp sil $1==$3 && $2==1 leaving lil $1 inc sil $1 pat lil adp sil $1==$3 && $2==1 leaving lil $1 inc sil $1
@ -2007,7 +1997,7 @@ pat loe ngi ste $1==$3 && $2==4
kills mem_nonlocals kills mem_nonlocals
gen neg {EXTERN, $1} gen neg {EXTERN, $1}
pat loe loe adp ste $1==$2 && $1==$4 pat loe dup adp ste $1==$4 && $2==4
uses REG={EXTERN,$1} yields %a uses REG={EXTERN,$1} yields %a
leaving loe $1 adp $3 ste $1 leaving loe $1 adp $3 ste $1

46
mach/i86/ncg/table
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@ -483,14 +483,8 @@ with AREG yields %1 %1
pat sdl ldl $1==$2 leaving dup 4 sdl $1 pat sdl ldl $1==$2 leaving dup 4 sdl $1
pat lol lol $1==$2
#ifdef REGVARS #ifdef REGVARS
&& inreg($1) <= 0 pat lol dup stl $2==2 && inreg($1) <= 0 && inreg($3) > 0
#endif
leaving lol $1 dup 2
#ifdef REGVARS
pat lol lol stl $1==$2 && inreg($1) <= 0 && inreg($3) > 0
kills regvar($3) kills regvar($3)
gen move {LOCAL,$1,2}, {LOCAL,$3,2} gen move {LOCAL,$1,2}, {LOCAL,$3,2}
yields {LOCAL,$3,2} yields {LOCAL,$3,2}
@ -510,10 +504,8 @@ with AREG yields %1 %1
pat sde lde $1==$2 leaving dup 4 sde $1 pat sde lde $1==$2 leaving dup 4 sde $1
pat loe loe $1==$2 leaving loe $1 dup 2
#ifdef REGVARS #ifdef REGVARS
pat loe loe stl $1==$2 && inreg($3) > 0 pat loe dup stl $2==2 && inreg($3) > 0
kills regvar($3) kills regvar($3)
gen move {EXTERN2,$1}, {LOCAL,$3,2} gen move {EXTERN2,$1}, {LOCAL,$3,2}
yields {LOCAL,$3,2} yields {LOCAL,$3,2}
@ -525,9 +517,7 @@ pat lil inreg($1) > 0 yields {ind_reg2, regvar($1)}
pat lil pat lil
uses ADDREG={LOCAL,$1,2} yields {ind_reg2,%a} uses ADDREG={LOCAL,$1,2} yields {ind_reg2,%a}
pat lil lil $1==$2 leaving lil $1 dup 2 pat lil dup stl $2==2 leaving lil $1 stl $3 lol $3
pat lil lil stl $1==$2 leaving lil $1 stl $3 lol $3
pat sil lil $1==$2 leaving dup 2 sil $1 pat sil lil $1==$2 leaving dup 2 sil $1
@ -1800,25 +1790,25 @@ gen neg {LOCAL, $1+2, 2}
neg {LOCAL, $1, 2} neg {LOCAL, $1, 2}
sbb {LOCAL, $1+2, 2}, {ANYCON, 0} sbb {LOCAL, $1+2, 2}, {ANYCON, 0}
pat lol lol adp stl loi stl $1==$2 && $2==$4 && $5<=2 pat lol dup adp stl loi stl $1==$4 && $2==2 && $5<=2
leaving lol $1 loi $5 stl $6 lol $2 adp $3 stl $4 leaving lol $1 loi $5 stl $6 lol $4 adp $3 stl $4
#ifdef REGVARS #ifdef REGVARS
pat lol lol adp stl loi $1==$2 && $2==$4 && $5==1 && inreg($1) > 0 pat lol dup adp stl loi $1==$4 && $2==2 && $5==1 && inreg($1) > 0
uses REG1 = {ind_reg1, regvar($1)} uses REG1 = {ind_reg1, regvar($1)}
yields %a yields %a
leaving lol $2 adp $3 stl $4 leaving lol $4 adp $3 stl $4
pat lol lol adp stl loi $1==$2 && $2==$4 && $5==2 && inreg($1) > 0 pat lol dup adp stl loi $1==$4 && $2==2 && $5==2 && inreg($1) > 0
uses REG = {ind_reg2, regvar($1)} uses REG = {ind_reg2, regvar($1)}
yields %a yields %a
leaving lol $2 adp $3 stl $4 leaving lol $4 adp $3 stl $4
pat adp stl inreg($2) > 0 leaving stl $2 lol $2 adp $1 stl $2 pat adp stl inreg($2) > 0 leaving stl $2 lol $2 adp $1 stl $2
#endif #endif
pat lol lol adp stl $1==$2 && $2==$4 pat lol dup adp stl $1==$4 && $2==2
uses ADDREG={LOCAL,$1,2} yields %a uses ADDREG={LOCAL,$1,2} yields %a
leaving lol $2 adp $3 stl $2 leaving lol $4 adp $3 stl $4
pat lol inl $1==$2 pat lol inl $1==$2
uses REG={LOCAL,$1,2} yields %a uses REG={LOCAL,$1,2} yields %a
@ -1843,20 +1833,20 @@ kills indexed,locals %ind+%size > $1 && %ind < $1+2
gen not {LOCAL, $1, 2} gen not {LOCAL, $1, 2}
#ifdef REGVARS #ifdef REGVARS
pat lil lil adp sil $1==$2 && $1==$4 && inreg($1)==reg_any pat lil dup adp sil $1==$4 && $2==2 && inreg($1)==reg_any
uses ADDREG={ind_reg2, regvar($1)} uses ADDREG={ind_reg2, regvar($1)}
yields %a yields %a
leaving lil $1 adp $3 sil $4 leaving lil $4 adp $3 sil $4
pat lil lil inc sil $1==$2 && $1==$4 && inreg($1)==reg_any pat lil dup inc sil $1==$4 && $2==2 && inreg($1)==reg_any
uses REG={ind_reg2, regvar($1)} uses REG={ind_reg2, regvar($1)}
yields %a yields %a
leaving lil $1 inc sil $4 leaving lil $4 inc sil $4
pat lil lil dec sil $1==$2 && $1==$4 && inreg($1)==reg_any pat lil dup dec sil $1==$4 && $2==2 && inreg($1)==reg_any
uses REG={ind_reg2, regvar($1)} uses REG={ind_reg2, regvar($1)}
yields %a yields %a
leaving lil $1 dec sil $4 leaving lil $4 dec sil $4
#endif #endif
pat lil adp sil $1==$3 && $2==1 leaving lil $1 inc sil $1 pat lil adp sil $1==$3 && $2==1 leaving lil $1 inc sil $1
@ -1993,7 +1983,7 @@ gen neg {EXTERN2, $1+2}
neg {EXTERN2, $1} neg {EXTERN2, $1}
sbb {EXTERN2, $1+2}, {ANYCON, 0} sbb {EXTERN2, $1+2}, {ANYCON, 0}
pat loe loe adp ste $1==$2 && $1==$4 pat loe dup adp ste $1==$4 && $2==2
uses ADDREG={EXTERN2,$1} yields %a uses ADDREG={EXTERN2,$1} yields %a
leaving loe $1 adp $3 ste $1 leaving loe $1 adp $3 ste $1

50
mach/m68020/ncg/table
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@ -1468,14 +1468,14 @@ pat lol loc lol adu stl $1==$3 && $3==$5 && $4==WORD_SIZE
killreg %a killreg %a
yields %a yields %a
pat lol lol loc sbu stl $1==$2 && $2==$5 && $4==WORD_SIZE && inreg($1)==reg_any pat lol dup loc sbu stl $1==$5 && $2==WORD_SIZE && $4==WORD_SIZE && inreg($1)==reg_any
kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any) kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
uses DD_REG = {LOCAL, $1} uses DD_REG = {LOCAL, $1}
gen sub_i {const, $3}, {LOCAL, $1} gen sub_i {const, $3}, {LOCAL, $1}
killreg %a killreg %a
yields %a yields %a
pat lol lol loc sbu stl $1==$2 && $2==$5 && $4==WORD_SIZE pat lol dup loc sbu stl $1==$5 && $2==WORD_SIZE && $4==WORD_SIZE
kills all_indir, LOCAL %bd==$1 kills all_indir, LOCAL %bd==$1
uses DD_REG = {LOCAL, $1} uses DD_REG = {LOCAL, $1}
gen sub_i {const, $3}, {LOCAL, $1} gen sub_i {const, $3}, {LOCAL, $1}
@ -1489,7 +1489,7 @@ pat loe loc loe adu ste $1==$3 && $3==$5 && $4==WORD_SIZE
killreg %a killreg %a
yields %a yields %a
pat loe loe loc sbu ste $1==$2 && $2==$5 && $4==WORD_SIZE pat loe dup loc sbu ste $1==$5 && $2==WORD_SIZE && $4==WORD_SIZE
kills posextern kills posextern
uses DD_REG = {absolute_int, $1} uses DD_REG = {absolute_int, $1}
gen sub_i {const,$3}, {absolute_int, $1} gen sub_i {const,$3}, {absolute_int, $1}
@ -1504,7 +1504,7 @@ pat lil loc lil adu sil $1==$3 && $3==$5 && $4==WORD_SIZE
killreg %a killreg %a
yields %a yields %a
pat lil lil loc sbu sil $1==$2 && $2==$5 && $4==WORD_SIZE pat lil dup loc sbu sil $1==$5 && $2==WORD_SIZE && $4==WORD_SIZE
&& inreg($1)==reg_pointer && inreg($1)==reg_pointer
kills allexceptcon kills allexceptcon
uses DD_REG = {indirect_int, regvar($1, reg_pointer)} uses DD_REG = {indirect_int, regvar($1, reg_pointer)}
@ -2500,14 +2500,14 @@ pat LLP ads SLP $1==$3 && $2==4 && inreg($1)==reg_pointer
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer) kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
gen add_l %1, {DLOCAL, $1} gen add_l %1, {DLOCAL, $1}
pat lil lil inc sil $1==$2 && $1==$4 && inreg($1)==reg_pointer pat lil dup inc sil $1==$4 && $2==WORD_SIZE && inreg($1)==reg_pointer
kills allexceptcon kills allexceptcon
uses DD_REG = {indirect_int, regvar($1, reg_pointer)} uses DD_REG = {indirect_int, regvar($1, reg_pointer)}
gen add_i {const, 1}, {indirect_int, regvar($1, reg_pointer)} gen add_i {const, 1}, {indirect_int, regvar($1, reg_pointer)}
killreg %a killreg %a
yields %a yields %a
pat lil lil dec sil $1==$2 && $1==$4 && inreg($1)==reg_pointer pat lil dup dec sil $1==$4 && $2==WORD_SIZE && inreg($1)==reg_pointer
kills allexceptcon kills allexceptcon
uses DD_REG = {indirect_int, regvar($1, reg_pointer)} uses DD_REG = {indirect_int, regvar($1, reg_pointer)}
gen sub_i {const, 1}, {indirect_int, regvar($1, reg_pointer)} gen sub_i {const, 1}, {indirect_int, regvar($1, reg_pointer)}
@ -2608,25 +2608,25 @@ pat lil loi dup adp lil sti $3==4 && $1==$5 && $2==4 && $6==4
yields %b yields %b
#endif #endif
pat LLP LLP adp SLP lae cmp $1==$2 && $2==$4 && inreg($1)==reg_pointer && $3 < 0 pat LLP dup adp SLP lae cmp $1==$4 && $2==4 && inreg($1)==reg_pointer && $3 < 0
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer) kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
gen sub_l {const4,0-$3},{DLOCAL,$1} gen sub_l {const4,0-$3},{DLOCAL,$1}
yields {DLOCAL,$1} {ext_addr, $5+$3} yields {DLOCAL,$1} {ext_addr, $5+$3}
leaving cmu 4 leaving cmu 4
pat LLP LLP adp SLP lae cmp $1==$2 && $2==$4 && inreg($1)==reg_pointer && $3 > 0 pat LLP dup adp SLP lae cmp $1==$4 && $2==4 && inreg($1)==reg_pointer && $3 > 0
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer) kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
gen add_l {const4,$3},{DLOCAL,$1} gen add_l {const4,$3},{DLOCAL,$1}
yields {DLOCAL,$1} {ext_addr, $5+$3} yields {DLOCAL,$1} {ext_addr, $5+$3}
leaving cmu 4 leaving cmu 4
pat LLP LLP adp SLP loi $1==$2 && $1==$4 && $3==4 && $5==4 && pat LLP dup adp SLP loi $1==$4 && $2==4 && $3==4 && $5==4 &&
inreg($1)==reg_pointer inreg($1)==reg_pointer
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer) kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
yields {post_inc4, regvar($1, reg_pointer)} yields {post_inc4, regvar($1, reg_pointer)}
pat LLP LLP adp SLP loi $1==$2 && $1==$4 && $3==$5 && inreg($1)==reg_pointer pat LLP dup adp SLP loi $1==$4 && $2==4 && $3==$5 && inreg($1)==reg_pointer
leaving LLP $1 loi $5 LLP $2 adp $3 SLP $4 leaving LLP $1 loi $5 LLP $4 adp $3 SLP $4
pat LLP loi LLP adp SLP $1==$3 && $1==$5 && $2==1 && $4==1 && pat LLP loi LLP adp SLP $1==$3 && $1==$5 && $2==1 && $4==1 &&
inreg($1)==reg_pointer inreg($1)==reg_pointer
@ -2648,8 +2648,8 @@ pat lil LLP adp SLP $1==$2 && $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer) kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
yields {post_inc_int, regvar($1, reg_pointer)} yields {post_inc_int, regvar($1, reg_pointer)}
pat LLP LLP adp SLP sti $1==$2 && $1==$4 && $3==$5 && inreg($1)==reg_pointer pat LLP dup adp SLP sti $1==$4 && $2==4 && $3==$5 && inreg($1)==reg_pointer
leaving LLP $1 sti $5 LLP $2 adp $3 SLP $4 leaving LLP $1 sti $5 LLP $4 adp $3 SLP $4
pat LLP sti LLP adp SLP $1==$3 && $1==$5 && $2==1 && $4==1 && pat LLP sti LLP adp SLP $1==$3 && $1==$5 && $2==1 && $4==1 &&
inreg($1)==reg_pointer inreg($1)==reg_pointer
@ -2670,7 +2670,7 @@ with any4
kills allexceptcon, regvar($1, reg_pointer) kills allexceptcon, regvar($1, reg_pointer)
gen move %1, {post_inc4, regvar($1, reg_pointer)} gen move %1, {post_inc4, regvar($1, reg_pointer)}
pat LLP LLP adp SLP sti $1==$2 && $1==$4 && $3==WORD_SIZE && $5==WORD_SIZE && pat LLP dup adp SLP sti $1==$4 && $2==4 && $3==WORD_SIZE && $5==WORD_SIZE &&
inreg($1)==reg_pointer inreg($1)==reg_pointer
with any_int-sconsts with any_int-sconsts
kills allexceptcon, regvar($1, reg_pointer) kills allexceptcon, regvar($1, reg_pointer)
@ -2728,42 +2728,42 @@ with any_int-sconsts
kills allexceptcon, regvar($1, reg_pointer) kills allexceptcon, regvar($1, reg_pointer)
gen move %1, {pre_dec_int, regvar($1, reg_pointer)} gen move %1, {pre_dec_int, regvar($1, reg_pointer)}
pat LLP LLP adp SLP $1==$2 && $1==$4 && inreg($1)==reg_pointer && directadd($3) pat LLP dup adp SLP $1==$4 && $2==4 && inreg($1)==reg_pointer && directadd($3)
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer) kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
uses AA_REG = {DLOCAL, $1} uses AA_REG = {DLOCAL, $1}
gen add_l {const4, $3}, {DLOCAL, $1} gen add_l {const4, $3}, {DLOCAL, $1}
killreg %a killreg %a
yields %a yields %a
pat LLP LLP adp SLP $1==$2 && $1==$4 && inreg($1)==reg_pointer && directsub($3) pat LLP dup adp SLP $1==$4 && $2==4 && inreg($1)==reg_pointer && directsub($3)
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer) kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
uses AA_REG = {DLOCAL, $1} uses AA_REG = {DLOCAL, $1}
gen sub_l {const4, 0-$3}, {DLOCAL, $1} gen sub_l {const4, 0-$3}, {DLOCAL, $1}
killreg %a killreg %a
yields %a yields %a
pat LLP LLP adp SLP $1==$2 && $1==$4 && inreg($1)==reg_pointer pat LLP dup adp SLP $1==$4 && $2==4 && inreg($1)==reg_pointer
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer) kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
uses AA_REG = {DLOCAL, $1}, DD_REG4 = {const4, $3} uses AA_REG = {DLOCAL, $1}, DD_REG4 = {const4, $3}
gen add_l %b, {DLOCAL, $1} gen add_l %b, {DLOCAL, $1}
killreg %a killreg %a
yields %a yields %a
pat LLP LLP adp SLP $1==$2 && $1==$4 && directadd($3) pat LLP dup adp SLP $1==$4 && $2==4 && directadd($3)
kills all_indir, DLOCAL %bd==$1 kills all_indir, DLOCAL %bd==$1
uses AA_REG = {DLOCAL, $1} uses AA_REG = {DLOCAL, $1}
gen add_l {const4, $3}, {DLOCAL, $1} gen add_l {const4, $3}, {DLOCAL, $1}
killreg %a killreg %a
yields %a yields %a
pat LLP LLP adp SLP $1==$2 && $1==$4 && directsub($3) pat LLP dup adp SLP $1==$4 && $2==4 && directsub($3)
kills all_indir, DLOCAL %bd==$1 kills all_indir, DLOCAL %bd==$1
uses AA_REG = {DLOCAL, $1} uses AA_REG = {DLOCAL, $1}
gen sub_l {const4, 0-$3}, {DLOCAL, $1} gen sub_l {const4, 0-$3}, {DLOCAL, $1}
killreg %a killreg %a
yields %a yields %a
pat LLP LLP adp SLP $1==$2 && $1==$4 pat LLP dup adp SLP $1==$4 && $2==4
kills all_indir, DLOCAL %bd==$1 kills all_indir, DLOCAL %bd==$1
uses AA_REG = {DLOCAL, $1}, DD_REG4 = {const4, $3} uses AA_REG = {DLOCAL, $1}, DD_REG4 = {const4, $3}
gen add_l %b, {DLOCAL, $1} gen add_l %b, {DLOCAL, $1}
@ -2797,7 +2797,7 @@ pat LLP adp SLP $1==$3
gen add_l %a, {DLOCAL, $1} gen add_l %a, {DLOCAL, $1}
#if WORD_SIZE!=2 #if WORD_SIZE!=2
pat lil lil adp sil sti $1==$2 && $1==$4 && inreg($1)==reg_pointer && $5<=4 pat lil dup adp sil sti $1==$4 && $2==4 && inreg($1)==reg_pointer && $5<=4
with conreg with conreg
kills allexceptcon kills allexceptcon
uses AA_REG = {indirect4, regvar($1, reg_pointer)} uses AA_REG = {indirect4, regvar($1, reg_pointer)}
@ -2805,14 +2805,14 @@ pat lil lil adp sil sti $1==$2 && $1==$4 && inreg($1)==reg_pointer && $5<=4
killreg %a killreg %a
yields %1 %a leaving sti $5 yields %1 %a leaving sti $5
pat lil lil adp sil $1==$2 && $1==$4 && inreg($1)==reg_pointer pat lil dup adp sil $1==$4 && $2==4 && inreg($1)==reg_pointer
kills allexceptcon kills allexceptcon
uses AA_REG = {indirect4, regvar($1, reg_pointer)} uses AA_REG = {indirect4, regvar($1, reg_pointer)}
gen add_l {const, $3}, {indirect4, regvar($1, reg_pointer)} gen add_l {const, $3}, {indirect4, regvar($1, reg_pointer)}
killreg %a killreg %a
yields %a yields %a
pat lil lil adp sil $1==$2 && $1==$4 pat lil dup adp sil $1==$4 && $2==4
kills allexceptcon kills allexceptcon
uses AA_REG, AA_REG = {LOCAL, $1} uses AA_REG, AA_REG = {LOCAL, $1}
gen move {indirect4, %b}, %a gen move {indirect4, %b}, %a
@ -2834,7 +2834,7 @@ pat lil adp sil $1==$3 && inreg($1)!=reg_any
#endif #endif
#endif /* WORD_SIZE==2 */ #endif /* WORD_SIZE==2 */
pat LEP LEP adp SEP $1==$2 && $1==$4 pat LEP dup adp SEP $1==$4 && $2==4
kills posextern kills posextern
uses AA_REG = {absolute4, $1} uses AA_REG = {absolute4, $1}
gen add_l {const4, $3}, {absolute4, $1} gen add_l {const4, $3}, {absolute4, $1}
@ -2895,8 +2895,6 @@ pat ldl yields {DLOCAL, $1}
pat loe yields {absolute_int, $1} pat loe yields {absolute_int, $1}
pat loe loe $1==$2 leaving loe $1 dup WORD_SIZE
/* replace ste loe by dup ste, but not if followed by a test ... */ /* replace ste loe by dup ste, but not if followed by a test ... */
proc steloezxx example ste loe zne proc steloezxx example ste loe zne
with any_int-sconsts with any_int-sconsts

50
mach/m68k2/ncg/table
View file

@ -1468,14 +1468,14 @@ pat lol loc lol adu stl $1==$3 && $3==$5 && $4==WORD_SIZE
killreg %a killreg %a
yields %a yields %a
pat lol lol loc sbu stl $1==$2 && $2==$5 && $4==WORD_SIZE && inreg($1)==reg_any pat lol dup loc sbu stl $1==$5 && $2==WORD_SIZE && $4==WORD_SIZE && inreg($1)==reg_any
kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any) kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
uses DD_REG = {LOCAL, $1} uses DD_REG = {LOCAL, $1}
gen sub_i {const, $3}, {LOCAL, $1} gen sub_i {const, $3}, {LOCAL, $1}
killreg %a killreg %a
yields %a yields %a
pat lol lol loc sbu stl $1==$2 && $2==$5 && $4==WORD_SIZE pat lol dup loc sbu stl $1==$5 && $2==WORD_SIZE && $4==WORD_SIZE
kills all_indir, LOCAL %bd==$1 kills all_indir, LOCAL %bd==$1
uses DD_REG = {LOCAL, $1} uses DD_REG = {LOCAL, $1}
gen sub_i {const, $3}, {LOCAL, $1} gen sub_i {const, $3}, {LOCAL, $1}
@ -1489,7 +1489,7 @@ pat loe loc loe adu ste $1==$3 && $3==$5 && $4==WORD_SIZE
killreg %a killreg %a
yields %a yields %a
pat loe loe loc sbu ste $1==$2 && $2==$5 && $4==WORD_SIZE pat loe dup loc sbu ste $1==$5 && $2==WORD_SIZE && $4==WORD_SIZE
kills posextern kills posextern
uses DD_REG = {absolute_int, $1} uses DD_REG = {absolute_int, $1}
gen sub_i {const,$3}, {absolute_int, $1} gen sub_i {const,$3}, {absolute_int, $1}
@ -1504,7 +1504,7 @@ pat lil loc lil adu sil $1==$3 && $3==$5 && $4==WORD_SIZE
killreg %a killreg %a
yields %a yields %a
pat lil lil loc sbu sil $1==$2 && $2==$5 && $4==WORD_SIZE pat lil dup loc sbu sil $1==$5 && $2==WORD_SIZE && $4==WORD_SIZE
&& inreg($1)==reg_pointer && inreg($1)==reg_pointer
kills allexceptcon kills allexceptcon
uses DD_REG = {indirect_int, regvar($1, reg_pointer)} uses DD_REG = {indirect_int, regvar($1, reg_pointer)}
@ -2500,14 +2500,14 @@ pat LLP ads SLP $1==$3 && $2==4 && inreg($1)==reg_pointer
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer) kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
gen add_l %1, {DLOCAL, $1} gen add_l %1, {DLOCAL, $1}
pat lil lil inc sil $1==$2 && $1==$4 && inreg($1)==reg_pointer pat lil dup inc sil $1==$4 && $2==WORD_SIZE && inreg($1)==reg_pointer
kills allexceptcon kills allexceptcon
uses DD_REG = {indirect_int, regvar($1, reg_pointer)} uses DD_REG = {indirect_int, regvar($1, reg_pointer)}
gen add_i {const, 1}, {indirect_int, regvar($1, reg_pointer)} gen add_i {const, 1}, {indirect_int, regvar($1, reg_pointer)}
killreg %a killreg %a
yields %a yields %a
pat lil lil dec sil $1==$2 && $1==$4 && inreg($1)==reg_pointer pat lil dup dec sil $1==$4 && $2==WORD_SIZE && inreg($1)==reg_pointer
kills allexceptcon kills allexceptcon
uses DD_REG = {indirect_int, regvar($1, reg_pointer)} uses DD_REG = {indirect_int, regvar($1, reg_pointer)}
gen sub_i {const, 1}, {indirect_int, regvar($1, reg_pointer)} gen sub_i {const, 1}, {indirect_int, regvar($1, reg_pointer)}
@ -2608,25 +2608,25 @@ pat lil loi dup adp lil sti $3==4 && $1==$5 && $2==4 && $6==4
yields %b yields %b
#endif #endif
pat LLP LLP adp SLP lae cmp $1==$2 && $2==$4 && inreg($1)==reg_pointer && $3 < 0 pat LLP dup adp SLP lae cmp $1==$4 && $2==4 && inreg($1)==reg_pointer && $3 < 0
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer) kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
gen sub_l {const4,0-$3},{DLOCAL,$1} gen sub_l {const4,0-$3},{DLOCAL,$1}
yields {DLOCAL,$1} {ext_addr, $5+$3} yields {DLOCAL,$1} {ext_addr, $5+$3}
leaving cmu 4 leaving cmu 4
pat LLP LLP adp SLP lae cmp $1==$2 && $2==$4 && inreg($1)==reg_pointer && $3 > 0 pat LLP dup adp SLP lae cmp $1==$4 && $2==4 && inreg($1)==reg_pointer && $3 > 0
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer) kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
gen add_l {const4,$3},{DLOCAL,$1} gen add_l {const4,$3},{DLOCAL,$1}
yields {DLOCAL,$1} {ext_addr, $5+$3} yields {DLOCAL,$1} {ext_addr, $5+$3}
leaving cmu 4 leaving cmu 4
pat LLP LLP adp SLP loi $1==$2 && $1==$4 && $3==4 && $5==4 && pat LLP dup adp SLP loi $1==$4 && $2==4 && $3==4 && $5==4 &&
inreg($1)==reg_pointer inreg($1)==reg_pointer
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer) kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
yields {post_inc4, regvar($1, reg_pointer)} yields {post_inc4, regvar($1, reg_pointer)}
pat LLP LLP adp SLP loi $1==$2 && $1==$4 && $3==$5 && inreg($1)==reg_pointer pat LLP dup adp SLP loi $1==$4 && $2==4 && $3==$5 && inreg($1)==reg_pointer
leaving LLP $1 loi $5 LLP $2 adp $3 SLP $4 leaving LLP $1 loi $5 LLP $4 adp $3 SLP $4
pat LLP loi LLP adp SLP $1==$3 && $1==$5 && $2==1 && $4==1 && pat LLP loi LLP adp SLP $1==$3 && $1==$5 && $2==1 && $4==1 &&
inreg($1)==reg_pointer inreg($1)==reg_pointer
@ -2648,8 +2648,8 @@ pat lil LLP adp SLP $1==$2 && $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer) kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
yields {post_inc_int, regvar($1, reg_pointer)} yields {post_inc_int, regvar($1, reg_pointer)}
pat LLP LLP adp SLP sti $1==$2 && $1==$4 && $3==$5 && inreg($1)==reg_pointer pat LLP dup adp SLP sti $1==$4 && $2==4 && $3==$5 && inreg($1)==reg_pointer
leaving LLP $1 sti $5 LLP $2 adp $3 SLP $4 leaving LLP $1 sti $5 LLP $4 adp $3 SLP $4
pat LLP sti LLP adp SLP $1==$3 && $1==$5 && $2==1 && $4==1 && pat LLP sti LLP adp SLP $1==$3 && $1==$5 && $2==1 && $4==1 &&
inreg($1)==reg_pointer inreg($1)==reg_pointer
@ -2670,7 +2670,7 @@ with any4
kills allexceptcon, regvar($1, reg_pointer) kills allexceptcon, regvar($1, reg_pointer)
gen move %1, {post_inc4, regvar($1, reg_pointer)} gen move %1, {post_inc4, regvar($1, reg_pointer)}
pat LLP LLP adp SLP sti $1==$2 && $1==$4 && $3==WORD_SIZE && $5==WORD_SIZE && pat LLP dup adp SLP sti $1==$4 && $2==4 && $3==WORD_SIZE && $5==WORD_SIZE &&
inreg($1)==reg_pointer inreg($1)==reg_pointer
with any_int-sconsts with any_int-sconsts
kills allexceptcon, regvar($1, reg_pointer) kills allexceptcon, regvar($1, reg_pointer)
@ -2728,42 +2728,42 @@ with any_int-sconsts
kills allexceptcon, regvar($1, reg_pointer) kills allexceptcon, regvar($1, reg_pointer)
gen move %1, {pre_dec_int, regvar($1, reg_pointer)} gen move %1, {pre_dec_int, regvar($1, reg_pointer)}
pat LLP LLP adp SLP $1==$2 && $1==$4 && inreg($1)==reg_pointer && directadd($3) pat LLP dup adp SLP $1==$4 && $2==4 && inreg($1)==reg_pointer && directadd($3)
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer) kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
uses AA_REG = {DLOCAL, $1} uses AA_REG = {DLOCAL, $1}
gen add_l {const4, $3}, {DLOCAL, $1} gen add_l {const4, $3}, {DLOCAL, $1}
killreg %a killreg %a
yields %a yields %a
pat LLP LLP adp SLP $1==$2 && $1==$4 && inreg($1)==reg_pointer && directsub($3) pat LLP dup adp SLP $1==$4 && $2==4 && inreg($1)==reg_pointer && directsub($3)
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer) kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
uses AA_REG = {DLOCAL, $1} uses AA_REG = {DLOCAL, $1}
gen sub_l {const4, 0-$3}, {DLOCAL, $1} gen sub_l {const4, 0-$3}, {DLOCAL, $1}
killreg %a killreg %a
yields %a yields %a
pat LLP LLP adp SLP $1==$2 && $1==$4 && inreg($1)==reg_pointer pat LLP dup adp SLP $1==$4 && $2==4 && inreg($1)==reg_pointer
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer) kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
uses AA_REG = {DLOCAL, $1}, DD_REG4 = {const4, $3} uses AA_REG = {DLOCAL, $1}, DD_REG4 = {const4, $3}
gen add_l %b, {DLOCAL, $1} gen add_l %b, {DLOCAL, $1}
killreg %a killreg %a
yields %a yields %a
pat LLP LLP adp SLP $1==$2 && $1==$4 && directadd($3) pat LLP dup adp SLP $1==$4 && $2==4 && directadd($3)
kills all_indir, DLOCAL %bd==$1 kills all_indir, DLOCAL %bd==$1
uses AA_REG = {DLOCAL, $1} uses AA_REG = {DLOCAL, $1}
gen add_l {const4, $3}, {DLOCAL, $1} gen add_l {const4, $3}, {DLOCAL, $1}
killreg %a killreg %a
yields %a yields %a
pat LLP LLP adp SLP $1==$2 && $1==$4 && directsub($3) pat LLP dup adp SLP $1==$4 && $2==4 && directsub($3)
kills all_indir, DLOCAL %bd==$1 kills all_indir, DLOCAL %bd==$1
uses AA_REG = {DLOCAL, $1} uses AA_REG = {DLOCAL, $1}
gen sub_l {const4, 0-$3}, {DLOCAL, $1} gen sub_l {const4, 0-$3}, {DLOCAL, $1}
killreg %a killreg %a
yields %a yields %a
pat LLP LLP adp SLP $1==$2 && $1==$4 pat LLP dup adp SLP $1==$4 && $2==4
kills all_indir, DLOCAL %bd==$1 kills all_indir, DLOCAL %bd==$1
uses AA_REG = {DLOCAL, $1}, DD_REG4 = {const4, $3} uses AA_REG = {DLOCAL, $1}, DD_REG4 = {const4, $3}
gen add_l %b, {DLOCAL, $1} gen add_l %b, {DLOCAL, $1}
@ -2797,7 +2797,7 @@ pat LLP adp SLP $1==$3
gen add_l %a, {DLOCAL, $1} gen add_l %a, {DLOCAL, $1}
#if WORD_SIZE!=2 #if WORD_SIZE!=2
pat lil lil adp sil sti $1==$2 && $1==$4 && inreg($1)==reg_pointer && $5<=4 pat lil dup adp sil sti $1==$4 && $2==4 && inreg($1)==reg_pointer && $5<=4
with conreg with conreg
kills allexceptcon kills allexceptcon
uses AA_REG = {indirect4, regvar($1, reg_pointer)} uses AA_REG = {indirect4, regvar($1, reg_pointer)}
@ -2805,14 +2805,14 @@ pat lil lil adp sil sti $1==$2 && $1==$4 && inreg($1)==reg_pointer && $5<=4
killreg %a killreg %a
yields %1 %a leaving sti $5 yields %1 %a leaving sti $5
pat lil lil adp sil $1==$2 && $1==$4 && inreg($1)==reg_pointer pat lil dup adp sil $1==$4 && $2==4 && inreg($1)==reg_pointer
kills allexceptcon kills allexceptcon
uses AA_REG = {indirect4, regvar($1, reg_pointer)} uses AA_REG = {indirect4, regvar($1, reg_pointer)}
gen add_l {const, $3}, {indirect4, regvar($1, reg_pointer)} gen add_l {const, $3}, {indirect4, regvar($1, reg_pointer)}
killreg %a killreg %a
yields %a yields %a
pat lil lil adp sil $1==$2 && $1==$4 pat lil dup adp sil $1==$4 && $2==4
kills allexceptcon kills allexceptcon
uses AA_REG, AA_REG = {LOCAL, $1} uses AA_REG, AA_REG = {LOCAL, $1}
gen move {indirect4, %b}, %a gen move {indirect4, %b}, %a
@ -2834,7 +2834,7 @@ pat lil adp sil $1==$3 && inreg($1)!=reg_any
#endif #endif
#endif /* WORD_SIZE==2 */ #endif /* WORD_SIZE==2 */
pat LEP LEP adp SEP $1==$2 && $1==$4 pat LEP dup adp SEP $1==$4 && $2==4
kills posextern kills posextern
uses AA_REG = {absolute4, $1} uses AA_REG = {absolute4, $1}
gen add_l {const4, $3}, {absolute4, $1} gen add_l {const4, $3}, {absolute4, $1}
@ -2895,8 +2895,6 @@ pat ldl yields {DLOCAL, $1}
pat loe yields {absolute_int, $1} pat loe yields {absolute_int, $1}
pat loe loe $1==$2 leaving loe $1 dup WORD_SIZE
/* replace ste loe by dup ste, but not if followed by a test ... */ /* replace ste loe by dup ste, but not if followed by a test ... */
proc steloezxx example ste loe zne proc steloezxx example ste loe zne
with any_int-sconsts with any_int-sconsts

50
mach/m68k4/ncg/table
View file

@ -1468,14 +1468,14 @@ pat lol loc lol adu stl $1==$3 && $3==$5 && $4==WORD_SIZE
killreg %a killreg %a
yields %a yields %a
pat lol lol loc sbu stl $1==$2 && $2==$5 && $4==WORD_SIZE && inreg($1)==reg_any pat lol dup loc sbu stl $1==$5 && $2==WORD_SIZE && $4==WORD_SIZE && inreg($1)==reg_any
kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any) kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
uses DD_REG = {LOCAL, $1} uses DD_REG = {LOCAL, $1}
gen sub_i {const, $3}, {LOCAL, $1} gen sub_i {const, $3}, {LOCAL, $1}
killreg %a killreg %a
yields %a yields %a
pat lol lol loc sbu stl $1==$2 && $2==$5 && $4==WORD_SIZE pat lol dup loc sbu stl $1==$5 && $2==WORD_SIZE && $4==WORD_SIZE
kills all_indir, LOCAL %bd==$1 kills all_indir, LOCAL %bd==$1
uses DD_REG = {LOCAL, $1} uses DD_REG = {LOCAL, $1}
gen sub_i {const, $3}, {LOCAL, $1} gen sub_i {const, $3}, {LOCAL, $1}
@ -1489,7 +1489,7 @@ pat loe loc loe adu ste $1==$3 && $3==$5 && $4==WORD_SIZE
killreg %a killreg %a
yields %a yields %a
pat loe loe loc sbu ste $1==$2 && $2==$5 && $4==WORD_SIZE pat loe dup loc sbu ste $1==$5 && $2==WORD_SIZE && $4==WORD_SIZE
kills posextern kills posextern
uses DD_REG = {absolute_int, $1} uses DD_REG = {absolute_int, $1}
gen sub_i {const,$3}, {absolute_int, $1} gen sub_i {const,$3}, {absolute_int, $1}
@ -1504,7 +1504,7 @@ pat lil loc lil adu sil $1==$3 && $3==$5 && $4==WORD_SIZE
killreg %a killreg %a
yields %a yields %a
pat lil lil loc sbu sil $1==$2 && $2==$5 && $4==WORD_SIZE pat lil dup loc sbu sil $1==$5 && $2==WORD_SIZE && $4==WORD_SIZE
&& inreg($1)==reg_pointer && inreg($1)==reg_pointer
kills allexceptcon kills allexceptcon
uses DD_REG = {indirect_int, regvar($1, reg_pointer)} uses DD_REG = {indirect_int, regvar($1, reg_pointer)}
@ -2500,14 +2500,14 @@ pat LLP ads SLP $1==$3 && $2==4 && inreg($1)==reg_pointer
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer) kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
gen add_l %1, {DLOCAL, $1} gen add_l %1, {DLOCAL, $1}
pat lil lil inc sil $1==$2 && $1==$4 && inreg($1)==reg_pointer pat lil dup inc sil $1==$4 && $2==WORD_SIZE && inreg($1)==reg_pointer
kills allexceptcon kills allexceptcon
uses DD_REG = {indirect_int, regvar($1, reg_pointer)} uses DD_REG = {indirect_int, regvar($1, reg_pointer)}
gen add_i {const, 1}, {indirect_int, regvar($1, reg_pointer)} gen add_i {const, 1}, {indirect_int, regvar($1, reg_pointer)}
killreg %a killreg %a
yields %a yields %a
pat lil lil dec sil $1==$2 && $1==$4 && inreg($1)==reg_pointer pat lil dup dec sil $1==$4 && $2==WORD_SIZE && inreg($1)==reg_pointer
kills allexceptcon kills allexceptcon
uses DD_REG = {indirect_int, regvar($1, reg_pointer)} uses DD_REG = {indirect_int, regvar($1, reg_pointer)}
gen sub_i {const, 1}, {indirect_int, regvar($1, reg_pointer)} gen sub_i {const, 1}, {indirect_int, regvar($1, reg_pointer)}
@ -2608,25 +2608,25 @@ pat lil loi dup adp lil sti $3==4 && $1==$5 && $2==4 && $6==4
yields %b yields %b
#endif #endif
pat LLP LLP adp SLP lae cmp $1==$2 && $2==$4 && inreg($1)==reg_pointer && $3 < 0 pat LLP dup adp SLP lae cmp $1==$4 && $2==4 && inreg($1)==reg_pointer && $3 < 0
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer) kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
gen sub_l {const4,0-$3},{DLOCAL,$1} gen sub_l {const4,0-$3},{DLOCAL,$1}
yields {DLOCAL,$1} {ext_addr, $5+$3} yields {DLOCAL,$1} {ext_addr, $5+$3}
leaving cmu 4 leaving cmu 4
pat LLP LLP adp SLP lae cmp $1==$2 && $2==$4 && inreg($1)==reg_pointer && $3 > 0 pat LLP dup adp SLP lae cmp $1==$4 && $2==4 && inreg($1)==reg_pointer && $3 > 0
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer) kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
gen add_l {const4,$3},{DLOCAL,$1} gen add_l {const4,$3},{DLOCAL,$1}
yields {DLOCAL,$1} {ext_addr, $5+$3} yields {DLOCAL,$1} {ext_addr, $5+$3}
leaving cmu 4 leaving cmu 4
pat LLP LLP adp SLP loi $1==$2 && $1==$4 && $3==4 && $5==4 && pat LLP dup adp SLP loi $1==$4 && $2==4 && $3==4 && $5==4 &&
inreg($1)==reg_pointer inreg($1)==reg_pointer
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer) kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
yields {post_inc4, regvar($1, reg_pointer)} yields {post_inc4, regvar($1, reg_pointer)}
pat LLP LLP adp SLP loi $1==$2 && $1==$4 && $3==$5 && inreg($1)==reg_pointer pat LLP dup adp SLP loi $1==$4 && $2==4 && $3==$5 && inreg($1)==reg_pointer
leaving LLP $1 loi $5 LLP $2 adp $3 SLP $4 leaving LLP $1 loi $5 LLP $4 adp $3 SLP $4
pat LLP loi LLP adp SLP $1==$3 && $1==$5 && $2==1 && $4==1 && pat LLP loi LLP adp SLP $1==$3 && $1==$5 && $2==1 && $4==1 &&
inreg($1)==reg_pointer inreg($1)==reg_pointer
@ -2648,8 +2648,8 @@ pat lil LLP adp SLP $1==$2 && $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer) kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
yields {post_inc_int, regvar($1, reg_pointer)} yields {post_inc_int, regvar($1, reg_pointer)}
pat LLP LLP adp SLP sti $1==$2 && $1==$4 && $3==$5 && inreg($1)==reg_pointer pat LLP dup adp SLP sti $1==$4 && $2==4 && $3==$5 && inreg($1)==reg_pointer
leaving LLP $1 sti $5 LLP $2 adp $3 SLP $4 leaving LLP $1 sti $5 LLP $4 adp $3 SLP $4
pat LLP sti LLP adp SLP $1==$3 && $1==$5 && $2==1 && $4==1 && pat LLP sti LLP adp SLP $1==$3 && $1==$5 && $2==1 && $4==1 &&
inreg($1)==reg_pointer inreg($1)==reg_pointer
@ -2670,7 +2670,7 @@ with any4
kills allexceptcon, regvar($1, reg_pointer) kills allexceptcon, regvar($1, reg_pointer)
gen move %1, {post_inc4, regvar($1, reg_pointer)} gen move %1, {post_inc4, regvar($1, reg_pointer)}
pat LLP LLP adp SLP sti $1==$2 && $1==$4 && $3==WORD_SIZE && $5==WORD_SIZE && pat LLP dup adp SLP sti $1==$4 && $2==4 && $3==WORD_SIZE && $5==WORD_SIZE &&
inreg($1)==reg_pointer inreg($1)==reg_pointer
with any_int-sconsts with any_int-sconsts
kills allexceptcon, regvar($1, reg_pointer) kills allexceptcon, regvar($1, reg_pointer)
@ -2728,42 +2728,42 @@ with any_int-sconsts
kills allexceptcon, regvar($1, reg_pointer) kills allexceptcon, regvar($1, reg_pointer)
gen move %1, {pre_dec_int, regvar($1, reg_pointer)} gen move %1, {pre_dec_int, regvar($1, reg_pointer)}
pat LLP LLP adp SLP $1==$2 && $1==$4 && inreg($1)==reg_pointer && directadd($3) pat LLP dup adp SLP $1==$4 && $2==4 && inreg($1)==reg_pointer && directadd($3)
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer) kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
uses AA_REG = {DLOCAL, $1} uses AA_REG = {DLOCAL, $1}
gen add_l {const4, $3}, {DLOCAL, $1} gen add_l {const4, $3}, {DLOCAL, $1}
killreg %a killreg %a
yields %a yields %a
pat LLP LLP adp SLP $1==$2 && $1==$4 && inreg($1)==reg_pointer && directsub($3) pat LLP dup adp SLP $1==$4 && $2==4 && inreg($1)==reg_pointer && directsub($3)
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer) kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
uses AA_REG = {DLOCAL, $1} uses AA_REG = {DLOCAL, $1}
gen sub_l {const4, 0-$3}, {DLOCAL, $1} gen sub_l {const4, 0-$3}, {DLOCAL, $1}
killreg %a killreg %a
yields %a yields %a
pat LLP LLP adp SLP $1==$2 && $1==$4 && inreg($1)==reg_pointer pat LLP dup adp SLP $1==$4 && $2==4 && inreg($1)==reg_pointer
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer) kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
uses AA_REG = {DLOCAL, $1}, DD_REG4 = {const4, $3} uses AA_REG = {DLOCAL, $1}, DD_REG4 = {const4, $3}
gen add_l %b, {DLOCAL, $1} gen add_l %b, {DLOCAL, $1}
killreg %a killreg %a
yields %a yields %a
pat LLP LLP adp SLP $1==$2 && $1==$4 && directadd($3) pat LLP dup adp SLP $1==$4 && $2==4 && directadd($3)
kills all_indir, DLOCAL %bd==$1 kills all_indir, DLOCAL %bd==$1
uses AA_REG = {DLOCAL, $1} uses AA_REG = {DLOCAL, $1}
gen add_l {const4, $3}, {DLOCAL, $1} gen add_l {const4, $3}, {DLOCAL, $1}
killreg %a killreg %a
yields %a yields %a
pat LLP LLP adp SLP $1==$2 && $1==$4 && directsub($3) pat LLP dup adp SLP $1==$4 && $2==4 && directsub($3)
kills all_indir, DLOCAL %bd==$1 kills all_indir, DLOCAL %bd==$1
uses AA_REG = {DLOCAL, $1} uses AA_REG = {DLOCAL, $1}
gen sub_l {const4, 0-$3}, {DLOCAL, $1} gen sub_l {const4, 0-$3}, {DLOCAL, $1}
killreg %a killreg %a
yields %a yields %a
pat LLP LLP adp SLP $1==$2 && $1==$4 pat LLP dup adp SLP $1==$4 && $2==4
kills all_indir, DLOCAL %bd==$1 kills all_indir, DLOCAL %bd==$1
uses AA_REG = {DLOCAL, $1}, DD_REG4 = {const4, $3} uses AA_REG = {DLOCAL, $1}, DD_REG4 = {const4, $3}
gen add_l %b, {DLOCAL, $1} gen add_l %b, {DLOCAL, $1}
@ -2797,7 +2797,7 @@ pat LLP adp SLP $1==$3
gen add_l %a, {DLOCAL, $1} gen add_l %a, {DLOCAL, $1}
#if WORD_SIZE!=2 #if WORD_SIZE!=2
pat lil lil adp sil sti $1==$2 && $1==$4 && inreg($1)==reg_pointer && $5<=4 pat lil dup adp sil sti $1==$4 && $2==4 && inreg($1)==reg_pointer && $5<=4
with conreg with conreg
kills allexceptcon kills allexceptcon
uses AA_REG = {indirect4, regvar($1, reg_pointer)} uses AA_REG = {indirect4, regvar($1, reg_pointer)}
@ -2805,14 +2805,14 @@ pat lil lil adp sil sti $1==$2 && $1==$4 && inreg($1)==reg_pointer && $5<=4
killreg %a killreg %a
yields %1 %a leaving sti $5 yields %1 %a leaving sti $5
pat lil lil adp sil $1==$2 && $1==$4 && inreg($1)==reg_pointer pat lil dup adp sil $1==$4 && $2==4 && inreg($1)==reg_pointer
kills allexceptcon kills allexceptcon
uses AA_REG = {indirect4, regvar($1, reg_pointer)} uses AA_REG = {indirect4, regvar($1, reg_pointer)}
gen add_l {const, $3}, {indirect4, regvar($1, reg_pointer)} gen add_l {const, $3}, {indirect4, regvar($1, reg_pointer)}
killreg %a killreg %a
yields %a yields %a
pat lil lil adp sil $1==$2 && $1==$4 pat lil dup adp sil $1==$4 && $2==4
kills allexceptcon kills allexceptcon
uses AA_REG, AA_REG = {LOCAL, $1} uses AA_REG, AA_REG = {LOCAL, $1}
gen move {indirect4, %b}, %a gen move {indirect4, %b}, %a
@ -2834,7 +2834,7 @@ pat lil adp sil $1==$3 && inreg($1)!=reg_any
#endif #endif
#endif /* WORD_SIZE==2 */ #endif /* WORD_SIZE==2 */
pat LEP LEP adp SEP $1==$2 && $1==$4 pat LEP dup adp SEP $1==$4 && $2==4
kills posextern kills posextern
uses AA_REG = {absolute4, $1} uses AA_REG = {absolute4, $1}
gen add_l {const4, $3}, {absolute4, $1} gen add_l {const4, $3}, {absolute4, $1}
@ -2895,8 +2895,6 @@ pat ldl yields {DLOCAL, $1}
pat loe yields {absolute_int, $1} pat loe yields {absolute_int, $1}
pat loe loe $1==$2 leaving loe $1 dup WORD_SIZE
/* replace ste loe by dup ste, but not if followed by a test ... */ /* replace ste loe by dup ste, but not if followed by a test ... */
proc steloezxx example ste loe zne proc steloezxx example ste loe zne
with any_int-sconsts with any_int-sconsts

50
mach/moon3/ncg/table
View file

@ -1468,14 +1468,14 @@ pat lol loc lol adu stl $1==$3 && $3==$5 && $4==WORD_SIZE
killreg %a killreg %a
yields %a yields %a
pat lol lol loc sbu stl $1==$2 && $2==$5 && $4==WORD_SIZE && inreg($1)==reg_any pat lol dup loc sbu stl $1==$5 && $2==WORD_SIZE && $4==WORD_SIZE && inreg($1)==reg_any
kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any) kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
uses DD_REG = {LOCAL, $1} uses DD_REG = {LOCAL, $1}
gen sub_i {const, $3}, {LOCAL, $1} gen sub_i {const, $3}, {LOCAL, $1}
killreg %a killreg %a
yields %a yields %a
pat lol lol loc sbu stl $1==$2 && $2==$5 && $4==WORD_SIZE pat lol dup loc sbu stl $1==$5 && $2==WORD_SIZE && $4==WORD_SIZE
kills all_indir, LOCAL %bd==$1 kills all_indir, LOCAL %bd==$1
uses DD_REG = {LOCAL, $1} uses DD_REG = {LOCAL, $1}
gen sub_i {const, $3}, {LOCAL, $1} gen sub_i {const, $3}, {LOCAL, $1}
@ -1489,7 +1489,7 @@ pat loe loc loe adu ste $1==$3 && $3==$5 && $4==WORD_SIZE
killreg %a killreg %a
yields %a yields %a
pat loe loe loc sbu ste $1==$2 && $2==$5 && $4==WORD_SIZE pat loe dup loc sbu ste $1==$5 && $2==WORD_SIZE && $4==WORD_SIZE
kills posextern kills posextern
uses DD_REG = {absolute_int, $1} uses DD_REG = {absolute_int, $1}
gen sub_i {const,$3}, {absolute_int, $1} gen sub_i {const,$3}, {absolute_int, $1}
@ -1504,7 +1504,7 @@ pat lil loc lil adu sil $1==$3 && $3==$5 && $4==WORD_SIZE
killreg %a killreg %a
yields %a yields %a
pat lil lil loc sbu sil $1==$2 && $2==$5 && $4==WORD_SIZE pat lil dup loc sbu sil $1==$5 && $2==WORD_SIZE && $4==WORD_SIZE
&& inreg($1)==reg_pointer && inreg($1)==reg_pointer
kills allexceptcon kills allexceptcon
uses DD_REG = {indirect_int, regvar($1, reg_pointer)} uses DD_REG = {indirect_int, regvar($1, reg_pointer)}
@ -2500,14 +2500,14 @@ pat LLP ads SLP $1==$3 && $2==4 && inreg($1)==reg_pointer
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer) kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
gen add_l %1, {DLOCAL, $1} gen add_l %1, {DLOCAL, $1}
pat lil lil inc sil $1==$2 && $1==$4 && inreg($1)==reg_pointer pat lil dup inc sil $1==$4 && $2==WORD_SIZE && inreg($1)==reg_pointer
kills allexceptcon kills allexceptcon
uses DD_REG = {indirect_int, regvar($1, reg_pointer)} uses DD_REG = {indirect_int, regvar($1, reg_pointer)}
gen add_i {const, 1}, {indirect_int, regvar($1, reg_pointer)} gen add_i {const, 1}, {indirect_int, regvar($1, reg_pointer)}
killreg %a killreg %a
yields %a yields %a
pat lil lil dec sil $1==$2 && $1==$4 && inreg($1)==reg_pointer pat lil dup dec sil $1==$4 && $2==WORD_SIZE && inreg($1)==reg_pointer
kills allexceptcon kills allexceptcon
uses DD_REG = {indirect_int, regvar($1, reg_pointer)} uses DD_REG = {indirect_int, regvar($1, reg_pointer)}
gen sub_i {const, 1}, {indirect_int, regvar($1, reg_pointer)} gen sub_i {const, 1}, {indirect_int, regvar($1, reg_pointer)}
@ -2608,25 +2608,25 @@ pat lil loi dup adp lil sti $3==4 && $1==$5 && $2==4 && $6==4
yields %b yields %b
#endif #endif
pat LLP LLP adp SLP lae cmp $1==$2 && $2==$4 && inreg($1)==reg_pointer && $3 < 0 pat LLP dup adp SLP lae cmp $1==$4 && $2==4 && inreg($1)==reg_pointer && $3 < 0
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer) kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
gen sub_l {const4,0-$3},{DLOCAL,$1} gen sub_l {const4,0-$3},{DLOCAL,$1}
yields {DLOCAL,$1} {ext_addr, $5+$3} yields {DLOCAL,$1} {ext_addr, $5+$3}
leaving cmu 4 leaving cmu 4
pat LLP LLP adp SLP lae cmp $1==$2 && $2==$4 && inreg($1)==reg_pointer && $3 > 0 pat LLP dup adp SLP lae cmp $1==$4 && $2==4 && inreg($1)==reg_pointer && $3 > 0
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer) kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
gen add_l {const4,$3},{DLOCAL,$1} gen add_l {const4,$3},{DLOCAL,$1}
yields {DLOCAL,$1} {ext_addr, $5+$3} yields {DLOCAL,$1} {ext_addr, $5+$3}
leaving cmu 4 leaving cmu 4
pat LLP LLP adp SLP loi $1==$2 && $1==$4 && $3==4 && $5==4 && pat LLP dup adp SLP loi $1==$4 && $2==4 && $3==4 && $5==4 &&
inreg($1)==reg_pointer inreg($1)==reg_pointer
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer) kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
yields {post_inc4, regvar($1, reg_pointer)} yields {post_inc4, regvar($1, reg_pointer)}
pat LLP LLP adp SLP loi $1==$2 && $1==$4 && $3==$5 && inreg($1)==reg_pointer pat LLP dup adp SLP loi $1==$4 && $2==4 && $3==$5 && inreg($1)==reg_pointer
leaving LLP $1 loi $5 LLP $2 adp $3 SLP $4 leaving LLP $1 loi $5 LLP $4 adp $3 SLP $4
pat LLP loi LLP adp SLP $1==$3 && $1==$5 && $2==1 && $4==1 && pat LLP loi LLP adp SLP $1==$3 && $1==$5 && $2==1 && $4==1 &&
inreg($1)==reg_pointer inreg($1)==reg_pointer
@ -2648,8 +2648,8 @@ pat lil LLP adp SLP $1==$2 && $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer) kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
yields {post_inc_int, regvar($1, reg_pointer)} yields {post_inc_int, regvar($1, reg_pointer)}
pat LLP LLP adp SLP sti $1==$2 && $1==$4 && $3==$5 && inreg($1)==reg_pointer pat LLP dup adp SLP sti $1==$4 && $2==4 && $3==$5 && inreg($1)==reg_pointer
leaving LLP $1 sti $5 LLP $2 adp $3 SLP $4 leaving LLP $1 sti $5 LLP $4 adp $3 SLP $4
pat LLP sti LLP adp SLP $1==$3 && $1==$5 && $2==1 && $4==1 && pat LLP sti LLP adp SLP $1==$3 && $1==$5 && $2==1 && $4==1 &&
inreg($1)==reg_pointer inreg($1)==reg_pointer
@ -2670,7 +2670,7 @@ with any4
kills allexceptcon, regvar($1, reg_pointer) kills allexceptcon, regvar($1, reg_pointer)
gen move %1, {post_inc4, regvar($1, reg_pointer)} gen move %1, {post_inc4, regvar($1, reg_pointer)}
pat LLP LLP adp SLP sti $1==$2 && $1==$4 && $3==WORD_SIZE && $5==WORD_SIZE && pat LLP dup adp SLP sti $1==$4 && $2==4 && $3==WORD_SIZE && $5==WORD_SIZE &&
inreg($1)==reg_pointer inreg($1)==reg_pointer
with any_int-sconsts with any_int-sconsts
kills allexceptcon, regvar($1, reg_pointer) kills allexceptcon, regvar($1, reg_pointer)
@ -2728,42 +2728,42 @@ with any_int-sconsts
kills allexceptcon, regvar($1, reg_pointer) kills allexceptcon, regvar($1, reg_pointer)
gen move %1, {pre_dec_int, regvar($1, reg_pointer)} gen move %1, {pre_dec_int, regvar($1, reg_pointer)}
pat LLP LLP adp SLP $1==$2 && $1==$4 && inreg($1)==reg_pointer && directadd($3) pat LLP dup adp SLP $1==$4 && $2==4 && inreg($1)==reg_pointer && directadd($3)
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer) kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
uses AA_REG = {DLOCAL, $1} uses AA_REG = {DLOCAL, $1}
gen add_l {const4, $3}, {DLOCAL, $1} gen add_l {const4, $3}, {DLOCAL, $1}
killreg %a killreg %a
yields %a yields %a
pat LLP LLP adp SLP $1==$2 && $1==$4 && inreg($1)==reg_pointer && directsub($3) pat LLP dup adp SLP $1==$4 && $2==4 && inreg($1)==reg_pointer && directsub($3)
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer) kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
uses AA_REG = {DLOCAL, $1} uses AA_REG = {DLOCAL, $1}
gen sub_l {const4, 0-$3}, {DLOCAL, $1} gen sub_l {const4, 0-$3}, {DLOCAL, $1}
killreg %a killreg %a
yields %a yields %a
pat LLP LLP adp SLP $1==$2 && $1==$4 && inreg($1)==reg_pointer pat LLP dup adp SLP $1==$4 && $2==4 && inreg($1)==reg_pointer
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer) kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
uses AA_REG = {DLOCAL, $1}, DD_REG4 = {const4, $3} uses AA_REG = {DLOCAL, $1}, DD_REG4 = {const4, $3}
gen add_l %b, {DLOCAL, $1} gen add_l %b, {DLOCAL, $1}
killreg %a killreg %a
yields %a yields %a
pat LLP LLP adp SLP $1==$2 && $1==$4 && directadd($3) pat LLP dup adp SLP $1==$4 && $2==4 && directadd($3)
kills all_indir, DLOCAL %bd==$1 kills all_indir, DLOCAL %bd==$1
uses AA_REG = {DLOCAL, $1} uses AA_REG = {DLOCAL, $1}
gen add_l {const4, $3}, {DLOCAL, $1} gen add_l {const4, $3}, {DLOCAL, $1}
killreg %a killreg %a
yields %a yields %a
pat LLP LLP adp SLP $1==$2 && $1==$4 && directsub($3) pat LLP dup adp SLP $1==$4 && $2==4 && directsub($3)
kills all_indir, DLOCAL %bd==$1 kills all_indir, DLOCAL %bd==$1
uses AA_REG = {DLOCAL, $1} uses AA_REG = {DLOCAL, $1}
gen sub_l {const4, 0-$3}, {DLOCAL, $1} gen sub_l {const4, 0-$3}, {DLOCAL, $1}
killreg %a killreg %a
yields %a yields %a
pat LLP LLP adp SLP $1==$2 && $1==$4 pat LLP dup adp SLP $1==$4 && $2==4
kills all_indir, DLOCAL %bd==$1 kills all_indir, DLOCAL %bd==$1
uses AA_REG = {DLOCAL, $1}, DD_REG4 = {const4, $3} uses AA_REG = {DLOCAL, $1}, DD_REG4 = {const4, $3}
gen add_l %b, {DLOCAL, $1} gen add_l %b, {DLOCAL, $1}
@ -2797,7 +2797,7 @@ pat LLP adp SLP $1==$3
gen add_l %a, {DLOCAL, $1} gen add_l %a, {DLOCAL, $1}
#if WORD_SIZE!=2 #if WORD_SIZE!=2
pat lil lil adp sil sti $1==$2 && $1==$4 && inreg($1)==reg_pointer && $5<=4 pat lil dup adp sil sti $1==$4 && $2==4 && inreg($1)==reg_pointer && $5<=4
with conreg with conreg
kills allexceptcon kills allexceptcon
uses AA_REG = {indirect4, regvar($1, reg_pointer)} uses AA_REG = {indirect4, regvar($1, reg_pointer)}
@ -2805,14 +2805,14 @@ pat lil lil adp sil sti $1==$2 && $1==$4 && inreg($1)==reg_pointer && $5<=4
killreg %a killreg %a
yields %1 %a leaving sti $5 yields %1 %a leaving sti $5
pat lil lil adp sil $1==$2 && $1==$4 && inreg($1)==reg_pointer pat lil dup adp sil $1==$4 && $2==4 && inreg($1)==reg_pointer
kills allexceptcon kills allexceptcon
uses AA_REG = {indirect4, regvar($1, reg_pointer)} uses AA_REG = {indirect4, regvar($1, reg_pointer)}
gen add_l {const, $3}, {indirect4, regvar($1, reg_pointer)} gen add_l {const, $3}, {indirect4, regvar($1, reg_pointer)}
killreg %a killreg %a
yields %a yields %a
pat lil lil adp sil $1==$2 && $1==$4 pat lil dup adp sil $1==$4 && $2==4
kills allexceptcon kills allexceptcon
uses AA_REG, AA_REG = {LOCAL, $1} uses AA_REG, AA_REG = {LOCAL, $1}
gen move {indirect4, %b}, %a gen move {indirect4, %b}, %a
@ -2834,7 +2834,7 @@ pat lil adp sil $1==$3 && inreg($1)!=reg_any
#endif #endif
#endif /* WORD_SIZE==2 */ #endif /* WORD_SIZE==2 */
pat LEP LEP adp SEP $1==$2 && $1==$4 pat LEP dup adp SEP $1==$4 && $2==4
kills posextern kills posextern
uses AA_REG = {absolute4, $1} uses AA_REG = {absolute4, $1}
gen add_l {const4, $3}, {absolute4, $1} gen add_l {const4, $3}, {absolute4, $1}
@ -2895,8 +2895,6 @@ pat ldl yields {DLOCAL, $1}
pat loe yields {absolute_int, $1} pat loe yields {absolute_int, $1}
pat loe loe $1==$2 leaving loe $1 dup WORD_SIZE
/* replace ste loe by dup ste, but not if followed by a test ... */ /* replace ste loe by dup ste, but not if followed by a test ... */
proc steloezxx example ste loe zne proc steloezxx example ste loe zne
with any_int-sconsts with any_int-sconsts

4
mach/ns/ncg/table
View file

@ -1153,12 +1153,12 @@ pat fef leaving loc 18 trp
* Group6 : pointer arithmetic * * Group6 : pointer arithmetic *
*****************************************************************/ *****************************************************************/
pat lol lol adp stl $1==$2 && $2==$4 pat lol dup adp stl $1==$4 && $2==4
kills allmincon kills allmincon
uses REG={LOCAL, $1} uses REG={LOCAL, $1}
gen addr {memrel4, fp, $1, $3}, {LOCAL, $1} yields %a gen addr {memrel4, fp, $1, $3}, {LOCAL, $1} yields %a
pat loe loe adp ste $1==$2 && $2==$4 pat loe dup adp ste $1==$4 && $2==4
kills allmincon kills allmincon
uses REG={absolute4, $1} uses REG={absolute4, $1}
gen addd {const4, $3}, {absolute4, $1} gen addd {const4, $3}, {absolute4, $1}

18
mach/pdp/cg/table
View file

@ -1063,17 +1063,17 @@ lol adi stl $2==2 && $1==$3 && inreg($1)==2 | source2 |
remove(regvar($1)) remove(regvar($1))
"add %[1],%(regvar($1)%)" "add %[1],%(regvar($1)%)"
erase(regvar($1)) | | | erase(regvar($1)) | | |
lol lol adp stl loi $1==$2 && $2==$4 && inreg($1)==2 && $3==1 && $5==1 | | lol dup adp stl loi $1==$4 && $2==2 && inreg($1)==2 && $3==1 && $5==1 | |
allocate(REG={CONST2, 0}) allocate(REG={CONST2, 0})
remove(regvar($1)) remove(regvar($1))
"bisb (%(regvar($1)%))+,%[a]" "bisb (%(regvar($1)%))+,%[a]"
erase(%[a]) | %[a] | | erase(%[a]) | %[a] | |
lol lol adp stl loi loc loc cii $1==$2 && $2==$4 && inreg($1)==2 && $3==1 && $5==1 && $6==1 && $7==2 | | lol dup adp stl loi loc loc cii $1==$4 && $2==2 && inreg($1)==2 && $3==1 && $5==1 && $6==1 && $7==2 | |
allocate(REG) allocate(REG)
remove(regvar($1)) remove(regvar($1))
"movb (%(regvar($1)%))+,%[a]" "movb (%(regvar($1)%))+,%[a]"
erase(%[a]) | %[a] | | erase(%[a]) | %[a] | |
lol lol adp stl loi $1==$2 && $2==$4 && inreg($1)==2 && $3==2 && $5==2 | | lol dup adp stl loi $1==$4 && $2==2 && inreg($1)==2 && $3==2 && $5==2 | |
allocate(REG) allocate(REG)
remove(regvar($1)) remove(regvar($1))
"mov (%(regvar($1)%))+,%[a]" | %[a] | | "mov (%(regvar($1)%))+,%[a]" | %[a] | |
@ -1083,12 +1083,12 @@ lol sti lol adp stl $1==$3 && $3==$5 && inreg($1)==2 && $2==1 && $4==1 | source1
sil lol adp stl $1==$2 && $2==$4 && inreg($1)==2 && $3==2 | source2 | sil lol adp stl $1==$2 && $2==$4 && inreg($1)==2 && $3==2 | source2 |
remove(regvar($1)) remove(regvar($1))
"mov %[1],(%(regvar($1)%))+" | | | "mov %[1],(%(regvar($1)%))+" | | |
lol lol adp stl $1==$2 && $2==$4 && inreg($1)==2 | | lol dup adp stl $1==$4 && $2==2 && inreg($1)==2 | |
allocate(REG=regvar($1)) | %[a] allocate(REG=regvar($1)) | %[a]
| lol $2 adp $3 stl $2 | | lol $1 adp $3 stl $1 |
lol lol adp stl $1==$2 && $2==$4 | | lol dup adp stl $1==$4 && $2==2 | |
allocate(REG={LOCAL2, $1, 2}) | %[a] allocate(REG={LOCAL2, $1, 2}) | %[a]
| lol $2 adp $3 stl $2 | | lol $1 adp $3 stl $1 |
lol inl $1==$2 && inreg($1)==2 | | lol inl $1==$2 && inreg($1)==2 | |
allocate(REG=regvar($1)) | %[a] allocate(REG=regvar($1)) | %[a]
| inl $2 | | inl $2 |
@ -1286,9 +1286,9 @@ loe ine $1==$2 | |
loe dee $1==$2 | | loe dee $1==$2 | |
allocate(REG={relative2, $1}) | %[a] allocate(REG={relative2, $1}) | %[a]
| dee $2 | | dee $2 |
loe loe adp ste $1==$2 && $2==$4 | | loe dup adp ste $1==$4 && $2==2 | |
allocate(REG={relative2, $1}) | %[a] allocate(REG={relative2, $1}) | %[a]
| loe $2 adp $3 ste $2 | | loe $1 adp $3 ste $1 |
#ifdef REGVARS #ifdef REGVARS
lol ior stl $2==2 && $1==$3 && inreg($1)==2 | source2 | lol ior stl $2==2 && $1==$3 && inreg($1)==2 | source2 |
remove(regvar($1)) remove(regvar($1))

26
mach/vax4/cg/table
View file

@ -1772,19 +1772,19 @@ dup adp loe sti $1==4 && $4==4
| %[a] %[1] {CONST4,$2} | %[a] %[1] {CONST4,$2}
| adi 4 loe $3 sti 4 | | adi 4 loe $3 sti 4 |
#ifdef REGVARS #ifdef REGVARS
lol lol adp stl loi $1==$4 && $2==$1 && inreg($1)==2 && $3==1 && $5==1 lol dup adp stl loi $1==$4 && $2==4 && inreg($1)==2 && $3==1 && $5==1
| | remove(regvar($1)) | | remove(regvar($1))
erase(regvar($1)) erase(regvar($1))
| {reginc1,regvar($1)} | | | {reginc1,regvar($1)} | |
lol lol adp stl loi $1==$4 && $2==$1 && inreg($1)==2 && $3==2 && $5==2 lol dup adp stl loi $1==$4 && $2==4 && inreg($1)==2 && $3==2 && $5==2
| | remove(regvar($1)) | | remove(regvar($1))
erase(regvar($1)) erase(regvar($1))
| {reginc2,regvar($1)} | | | {reginc2,regvar($1)} | |
lol lol adp stl loi $1==$4 && $2==$1 && inreg($1)==2 && $3==4 && $5==4 lol dup adp stl loi $1==$4 && $2==4 && inreg($1)==2 && $3==4 && $5==4
| | remove(regvar($1)) | | remove(regvar($1))
erase(regvar($1)) erase(regvar($1))
| {reginc4,regvar($1)} | | | {reginc4,regvar($1)} | |
lol lol adp stl loi $1==$4 && $2==$1 && inreg($1)==2 && $3==8 && $5==8 lol dup adp stl loi $1==$4 && $2==4 && inreg($1)==2 && $3==8 && $5==8
| | remove(regvar($1)) | | remove(regvar($1))
erase(regvar($1)) erase(regvar($1))
| {reginc8,regvar($1)} | | | {reginc8,regvar($1)} | |
@ -1804,7 +1804,7 @@ lol adp dup stl loi $1==$4 && $2==(0-8) && inreg($1)==2 && $3==4 && $5==8
| | remove(regvar($1)) | | remove(regvar($1))
erase(regvar($1)) erase(regvar($1))
| {regdec8,regvar($1)} | | | {regdec8,regvar($1)} | |
lol lol adp stl sti $1==$4 && $2==$1 && inreg($1)==2 && $3==1 && $5==1 lol dup adp stl sti $1==$4 && $2==4 && inreg($1)==2 && $3==1 && $5==1
| NC source1 | | NC source1 |
REMEXTANDLOC REMEXTANDLOC
remove(regvar($1)) remove(regvar($1))
@ -1820,7 +1820,7 @@ lol lol adp stl sti $1==$4 && $2==$1 && inreg($1)==2 && $3==1 && $5==1
remove(regvar($1)) remove(regvar($1))
"cvtlb\t%[1],(%(regvar($1)%))+" "cvtlb\t%[1],(%(regvar($1)%))+"
erase(regvar($1)) | | | (3,7)+%[1] erase(regvar($1)) | | | (3,7)+%[1]
lol lol adp stl sti $1==$4 && $2==$1 && inreg($1)==2 && $3==2 && $5==2 lol dup adp stl sti $1==$4 && $2==4 && inreg($1)==2 && $3==2 && $5==2
| NC source2 | | NC source2 |
REMEXTANDLOC REMEXTANDLOC
remove(regvar($1)) remove(regvar($1))
@ -1831,13 +1831,13 @@ lol lol adp stl sti $1==$4 && $2==$1 && inreg($1)==2 && $3==2 && $5==2
remove(regvar($1)) remove(regvar($1))
"cvtlw\t%[1],(%(regvar($1)%))+" "cvtlw\t%[1],(%(regvar($1)%))+"
erase(regvar($1)) | | | (3,7)+%[1] erase(regvar($1)) | | | (3,7)+%[1]
lol lol adp stl sti $1==$4 && $2==$1 && inreg($1)==2 && $3==4 && $5==4 lol dup adp stl sti $1==$4 && $2==4 && inreg($1)==2 && $3==4 && $5==4
| source4 | | source4 |
REMEXTANDLOC REMEXTANDLOC
remove(regvar($1)) remove(regvar($1))
move(%[1],{reginc4,regvar($1)}) move(%[1],{reginc4,regvar($1)})
erase(regvar($1)) | | | erase(regvar($1)) | | |
lol lol adp stl sti $1==$4 && $2==$1 && inreg($1)==2 && $3==8 && $5==8 lol dup adp stl sti $1==$4 && $2==4 && inreg($1)==2 && $3==8 && $5==8
| source8 | | source8 |
REMEXTANDLOC REMEXTANDLOC
remove(regvar($1)) remove(regvar($1))
@ -1882,7 +1882,7 @@ lol adp dup stl sti $1==$4 && inreg($1)==2 && $2==(0-8) && $3==4 && $5==8
remove(regvar($1)) remove(regvar($1))
move(%[1],{regdec8,regvar($1)}) move(%[1],{regdec8,regvar($1)})
erase(regvar($1)) | | | erase(regvar($1)) | | |
lol lol adp stl $1==$4 && $2==$4 && inreg($1)==2 lol dup adp stl $1==$4 && $2==4 && inreg($1)==2
| | remove(regvar($1)) | | remove(regvar($1))
allocate(REG=regvar($1)) allocate(REG=regvar($1))
"addl2\t$$$3,%(regvar($1)%)" "addl2\t$$$3,%(regvar($1)%)"
@ -1902,20 +1902,20 @@ lol adp stl $1==$3 && $1>=0
remove(LOCALS,%[num]<=$1+3 && %[num]+%[size]>$1) remove(LOCALS,%[num]<=$1+3 && %[num]+%[size]>$1)
"addl2\t$$$2,$1(ap)" "addl2\t$$$2,$1(ap)"
setcc({LOCAL4,AP,$1,4}) | | | setcc({LOCAL4,AP,$1,4}) | | |
lol lol adp stl $1==$4 && $2==$4 && $2<0 lol dup adp stl $1==$4 && $2==4 && $1<0
| | remove(displaced) | | remove(displaced)
remove(LOCALS,%[num]<=$1+3 && %[num]+%[size]>$1) remove(LOCALS,%[num]<=$1+3 && %[num]+%[size]>$1)
allocate(REG={LOCAL4,LB,$1,4}) allocate(REG={LOCAL4,LB,$1,4})
"addl2\t$$$3,$1(fp)" "addl2\t$$$3,$1(fp)"
setcc({LOCAL4,LB,$1,4}) | %[a] | | setcc({LOCAL4,LB,$1,4}) | %[a] | |
lol lol adp stl $1==$4 && $2==$4 lol dup adp stl $1==$4 && $2==4
| | remove(displaced) | | remove(displaced)
remove(LOCALS,%[num]<=$1+3 && %[num]+%[size]>$1) remove(LOCALS,%[num]<=$1+3 && %[num]+%[size]>$1)
allocate(REG={LOCAL4,AP,$1,4}) allocate(REG={LOCAL4,AP,$1,4})
"addl2\t$$$3,$1(ap)" "addl2\t$$$3,$1(ap)"
setcc({LOCAL4,AP,$1,4}) | %[a] | | setcc({LOCAL4,AP,$1,4}) | %[a] | |
#ifdef REGVARS #ifdef REGVARS
lil lil adp sil $1==$2 && $1==$4 && inreg($1)==2 lil dup adp sil $1==$4 && $2==4 && inreg($1)==2
| | REMEXTANDLOC | | REMEXTANDLOC
allocate(REG={regdef4,regvar($1)}) allocate(REG={regdef4,regvar($1)})
"addl2\t$$$3,(%(regvar($1)%))" "addl2\t$$$3,(%(regvar($1)%))"
@ -1929,7 +1929,7 @@ lol lof dup adp lol stf $1==$5 && $2==$6 && $3==4 && inreg($1)==2
loe adp ste $1==$3 loe adp ste $1==$3
| | remove(externals) | | remove(externals)
"addl2\t$$$2,$1" | | | "addl2\t$$$2,$1" | | |
loe loe adp ste $1==$4 && $2==$1 loe dup adp ste $1==$4 && $2==4
| | remove(externals) | | remove(externals)
allocate(REG={EXTERNAL4,$1}) allocate(REG={EXTERNAL4,$1})
"addl2\t$$$3,$1" | %[a] | | "addl2\t$$$3,$1" | %[a] | |