fixed some strange constructions
This commit is contained in:
eck
parent
8401d7b9ec
commit
dc500c3463
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@ -29,7 +29,8 @@ Something very wrong here!
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*/
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#define small(x) ((x)>=1 && (x)<=8)
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#define abs_small(x) ((x)>=0-8 && (x)<=8)
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#define directadd(x) (small(x) || (x)>128)
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#define directsub(x) (directadd(0-x))
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#define nicesize(x) ((x)==1||(x)==2||(x)==4||(x)==8)
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#define low8(x) ((x) & 0377)
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#define low16(x) ((x) & 0177777)
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@ -49,11 +50,11 @@ TIMEFACTOR = 1/2
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PROPERTIES
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D_REG /* data registers */
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A_REG(EM_PSIZE) /* address registers */
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A_REG(4) /* address registers */
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DD_REG /* allocatable D_REG, may not be a register variable */
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AA_REG(EM_PSIZE) /* allocatable A_REG, may not be a register variable */
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AA_REG(4) /* allocatable A_REG, may not be a register variable */
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RD_REG /* data register, register var */
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RA_REG(EM_PSIZE) /* address register, register var */
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RA_REG(4) /* address register, register var */
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#if WORD_SIZE==2
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D_REG4(4) /* data register, 4 bytes */
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DD_REG4(4) /* allocatable D_REG, 4 bytes */
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@ -2603,31 +2604,31 @@ pat LLP sti LLP adp SLP $1==$3 && $1==$5 && $2==1 && $4==1 &&
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inreg($1)==reg_pointer
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with any1
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kills allexceptcon, regvar($1, reg_pointer)
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gen move_b %1, {post_inc1, regvar($1, reg_pointer)}
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gen move %1, {post_inc1, regvar($1, reg_pointer)}
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/* Normally, LLP sti will ve optimzed into sil */
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pat LLP sti LLP adp SLP $1==$3 && $1==$5 && $2==2 && $4==2 &&
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inreg($1)==reg_pointer
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with any2
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kills allexceptcon, regvar($1, reg_pointer)
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gen move_w %1, {post_inc2, regvar($1, reg_pointer)}
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gen move %1, {post_inc2, regvar($1, reg_pointer)}
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pat LLP sti LLP adp SLP $1==$3 && $1==$5 && $2==4 && $4==4 &&
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inreg($1)==reg_pointer
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with any4
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kills allexceptcon, regvar($1, reg_pointer)
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gen move_l %1, {post_inc4, regvar($1, reg_pointer)}
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gen move %1, {post_inc4, regvar($1, reg_pointer)}
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pat LLP LLP adp SLP sti $1==$2 && $1==$4 && $3==WORD_SIZE && $5==WORD_SIZE &&
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inreg($1)==reg_pointer
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with any_int-sconsts
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kills allexceptcon, regvar($1, reg_pointer)
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gen move_i %1, {post_inc_int, regvar($1, reg_pointer)}
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gen move %1, {post_inc_int, regvar($1, reg_pointer)}
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pat sil LLP adp SLP $1==$2 && $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer
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with any_int-sconsts
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kills allexceptcon, regvar($1, reg_pointer)
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gen move_i %1, {post_inc_int, regvar($1, reg_pointer)}
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gen move %1, {post_inc_int, regvar($1, reg_pointer)}
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pat LLP adp SLP LLP loi $1==$3 && $1==$4 && $2==0-1 && $5==1 &&
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inreg($1)==reg_pointer
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@ -2654,35 +2655,42 @@ pat LLP adp SLP LLP sti $1==$3 && $1==$4 && $2==0-1 && $5==1 &&
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inreg($1)==reg_pointer
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with any1
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kills allexceptcon, regvar($1, reg_pointer)
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gen move_b %1, {pre_dec1, regvar($1, reg_pointer)}
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gen move %1, {pre_dec1, regvar($1, reg_pointer)}
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#if WORD_SIZE!=2
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pat LLP adp SLP LLP sti $1==$3 && $1==$4 && $2==0-2 && $5==2 &&
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inreg($1)==reg_pointer
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with any2
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kills allexceptcon, regvar($1, reg_pointer)
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gen move_w %1, {pre_dec2, regvar($1, reg_pointer)}
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gen move %1, {pre_dec2, regvar($1, reg_pointer)}
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#else
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pat LLP adp SLP LLP sti $1==$3 && $1==$4 && $2==0-4 && $5==4 &&
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inreg($1)==reg_pointer
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with any4
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kills allexceptcon, regvar($1, reg_pointer)
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gen move_l %1, {pre_dec4, regvar($1, reg_pointer)}
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gen move %1, {pre_dec4, regvar($1, reg_pointer)}
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#endif
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pat LLP adp SLP sil $1==$3 && $1==$4 && $2==0-WORD_SIZE &&
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inreg($1)==reg_pointer
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with any_int-sconsts
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kills allexceptcon, regvar($1, reg_pointer)
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gen move_i %1, {pre_dec_int, regvar($1, reg_pointer)}
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gen move %1, {pre_dec_int, regvar($1, reg_pointer)}
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pat LLP LLP adp SLP $1==$2 && $1==$4 && inreg($1)==reg_pointer && abs_small($3)
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pat LLP LLP adp SLP $1==$2 && $1==$4 && inreg($1)==reg_pointer && directadd($3)
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kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
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uses AA_REG = {DLOCAL, $1}
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gen add_l {const4, $3}, {DLOCAL, $1}
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killreg %a
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yields %a
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pat LLP LLP adp SLP $1==$2 && $1==$4 && inreg($1)==reg_pointer && directsub($3)
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kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
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uses AA_REG = {DLOCAL, $1}
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gen sub_l {const4, 0-$3}, {DLOCAL, $1}
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killreg %a
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yields %a
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pat LLP LLP adp SLP $1==$2 && $1==$4 && inreg($1)==reg_pointer
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kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
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uses AA_REG = {DLOCAL, $1}, DD_REG4 = {const4, $3}
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@ -2690,37 +2698,52 @@ pat LLP LLP adp SLP $1==$2 && $1==$4 && inreg($1)==reg_pointer
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killreg %a
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yields %a
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pat LLP LLP adp SLP $1==$2 && $1==$4 && abs_small($3)
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kills all_indir, DLOCAL %bd==$1
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uses AA_REG = {DLOCAL, $1}, DD_REG4 = {const4, $3}
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gen add_l %b, {DLOCAL, $1}
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killreg %a
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yields %a
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pat LLP LLP adp SLP $1==$2 && $1==$4
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pat LLP LLP adp SLP $1==$2 && $1==$4 && directadd($3)
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kills all_indir, DLOCAL %bd==$1
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uses AA_REG = {DLOCAL, $1}
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gen add_l {const4, $3}, {DLOCAL, $1}
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killreg %a
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yields %a
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pat LLP adp SLP $1==$3 && inreg($1)==reg_pointer && abs_small($2)
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pat LLP LLP adp SLP $1==$2 && $1==$4 && directsub($3)
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kills all_indir, DLOCAL %bd==$1
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uses AA_REG = {DLOCAL, $1}
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gen sub_l {const4, 0-$3}, {DLOCAL, $1}
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killreg %a
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yields %a
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pat LLP LLP adp SLP $1==$2 && $1==$4
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kills all_indir, DLOCAL %bd==$1
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uses AA_REG = {DLOCAL, $1}, DD_REG4 = {const4, $3}
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gen add_l %b, {DLOCAL, $1}
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killreg %a
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yields %a
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pat LLP adp SLP $1==$3 && inreg($1)==reg_pointer && directadd($2)
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kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
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gen add_l {const4, $2}, {DLOCAL, $1}
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pat LLP adp SLP $1==$3 && inreg($1)==reg_pointer && directsub($2)
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kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
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gen sub_l {const4, 0-$2}, {DLOCAL, $1}
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pat LLP adp SLP $1==$3 && inreg($1)==reg_pointer
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kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
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uses DD_REG4 = {const4, $2}
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gen add_l %a, {DLOCAL, $1}
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pat LLP adp SLP $1==$3 && abs_small($2)
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pat LLP adp SLP $1==$3 && directadd($2)
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kills all_indir, DLOCAL %bd==$1
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uses DD_REG4 = {const4, $2}
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gen add_l %a, {DLOCAL, $1}
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gen add_l {const4, $2}, {DLOCAL, $1}
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pat LLP adp SLP $1==$3 && directsub($2)
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kills all_indir, DLOCAL %bd==$1
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gen sub_l {const4, 0-$2}, {DLOCAL, $1}
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pat LLP adp SLP $1==$3
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kills all_indir, DLOCAL %bd==$1
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gen add_l {const4, $2}, {DLOCAL, $1}
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uses DD_REG4 = {const4, $2}
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gen add_l %a, {DLOCAL, $1}
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#if WORD_SIZE!=2
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pat lil lil adp sil sti $1==$2 && $1==$4 && inreg($1)==reg_pointer && $5<=4
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@ -29,7 +29,8 @@ Something very wrong here!
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*/
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#define small(x) ((x)>=1 && (x)<=8)
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#define abs_small(x) ((x)>=0-8 && (x)<=8)
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#define directadd(x) (small(x) || (x)>128)
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#define directsub(x) (directadd(0-x))
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#define nicesize(x) ((x)==1||(x)==2||(x)==4||(x)==8)
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#define low8(x) ((x) & 0377)
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#define low16(x) ((x) & 0177777)
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@ -49,11 +50,11 @@ TIMEFACTOR = 1/2
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PROPERTIES
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D_REG /* data registers */
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A_REG(EM_PSIZE) /* address registers */
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A_REG(4) /* address registers */
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DD_REG /* allocatable D_REG, may not be a register variable */
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AA_REG(EM_PSIZE) /* allocatable A_REG, may not be a register variable */
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AA_REG(4) /* allocatable A_REG, may not be a register variable */
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RD_REG /* data register, register var */
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RA_REG(EM_PSIZE) /* address register, register var */
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RA_REG(4) /* address register, register var */
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#if WORD_SIZE==2
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D_REG4(4) /* data register, 4 bytes */
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DD_REG4(4) /* allocatable D_REG, 4 bytes */
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@ -2603,31 +2604,31 @@ pat LLP sti LLP adp SLP $1==$3 && $1==$5 && $2==1 && $4==1 &&
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inreg($1)==reg_pointer
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with any1
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kills allexceptcon, regvar($1, reg_pointer)
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gen move_b %1, {post_inc1, regvar($1, reg_pointer)}
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gen move %1, {post_inc1, regvar($1, reg_pointer)}
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/* Normally, LLP sti will ve optimzed into sil */
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pat LLP sti LLP adp SLP $1==$3 && $1==$5 && $2==2 && $4==2 &&
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inreg($1)==reg_pointer
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with any2
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kills allexceptcon, regvar($1, reg_pointer)
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gen move_w %1, {post_inc2, regvar($1, reg_pointer)}
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gen move %1, {post_inc2, regvar($1, reg_pointer)}
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pat LLP sti LLP adp SLP $1==$3 && $1==$5 && $2==4 && $4==4 &&
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inreg($1)==reg_pointer
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with any4
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kills allexceptcon, regvar($1, reg_pointer)
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gen move_l %1, {post_inc4, regvar($1, reg_pointer)}
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gen move %1, {post_inc4, regvar($1, reg_pointer)}
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pat LLP LLP adp SLP sti $1==$2 && $1==$4 && $3==WORD_SIZE && $5==WORD_SIZE &&
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inreg($1)==reg_pointer
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with any_int-sconsts
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kills allexceptcon, regvar($1, reg_pointer)
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gen move_i %1, {post_inc_int, regvar($1, reg_pointer)}
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gen move %1, {post_inc_int, regvar($1, reg_pointer)}
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pat sil LLP adp SLP $1==$2 && $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer
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with any_int-sconsts
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kills allexceptcon, regvar($1, reg_pointer)
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gen move_i %1, {post_inc_int, regvar($1, reg_pointer)}
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gen move %1, {post_inc_int, regvar($1, reg_pointer)}
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pat LLP adp SLP LLP loi $1==$3 && $1==$4 && $2==0-1 && $5==1 &&
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inreg($1)==reg_pointer
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@ -2654,35 +2655,42 @@ pat LLP adp SLP LLP sti $1==$3 && $1==$4 && $2==0-1 && $5==1 &&
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inreg($1)==reg_pointer
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with any1
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kills allexceptcon, regvar($1, reg_pointer)
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gen move_b %1, {pre_dec1, regvar($1, reg_pointer)}
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gen move %1, {pre_dec1, regvar($1, reg_pointer)}
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#if WORD_SIZE!=2
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pat LLP adp SLP LLP sti $1==$3 && $1==$4 && $2==0-2 && $5==2 &&
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inreg($1)==reg_pointer
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with any2
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kills allexceptcon, regvar($1, reg_pointer)
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gen move_w %1, {pre_dec2, regvar($1, reg_pointer)}
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gen move %1, {pre_dec2, regvar($1, reg_pointer)}
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#else
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pat LLP adp SLP LLP sti $1==$3 && $1==$4 && $2==0-4 && $5==4 &&
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inreg($1)==reg_pointer
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with any4
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kills allexceptcon, regvar($1, reg_pointer)
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gen move_l %1, {pre_dec4, regvar($1, reg_pointer)}
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gen move %1, {pre_dec4, regvar($1, reg_pointer)}
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#endif
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pat LLP adp SLP sil $1==$3 && $1==$4 && $2==0-WORD_SIZE &&
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inreg($1)==reg_pointer
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with any_int-sconsts
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kills allexceptcon, regvar($1, reg_pointer)
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gen move_i %1, {pre_dec_int, regvar($1, reg_pointer)}
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gen move %1, {pre_dec_int, regvar($1, reg_pointer)}
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pat LLP LLP adp SLP $1==$2 && $1==$4 && inreg($1)==reg_pointer && abs_small($3)
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pat LLP LLP adp SLP $1==$2 && $1==$4 && inreg($1)==reg_pointer && directadd($3)
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kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
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uses AA_REG = {DLOCAL, $1}
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gen add_l {const4, $3}, {DLOCAL, $1}
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killreg %a
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yields %a
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pat LLP LLP adp SLP $1==$2 && $1==$4 && inreg($1)==reg_pointer && directsub($3)
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kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
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uses AA_REG = {DLOCAL, $1}
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gen sub_l {const4, 0-$3}, {DLOCAL, $1}
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killreg %a
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yields %a
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pat LLP LLP adp SLP $1==$2 && $1==$4 && inreg($1)==reg_pointer
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kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
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uses AA_REG = {DLOCAL, $1}, DD_REG4 = {const4, $3}
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@ -2690,37 +2698,52 @@ pat LLP LLP adp SLP $1==$2 && $1==$4 && inreg($1)==reg_pointer
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killreg %a
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yields %a
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pat LLP LLP adp SLP $1==$2 && $1==$4 && abs_small($3)
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kills all_indir, DLOCAL %bd==$1
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uses AA_REG = {DLOCAL, $1}, DD_REG4 = {const4, $3}
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gen add_l %b, {DLOCAL, $1}
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killreg %a
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yields %a
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pat LLP LLP adp SLP $1==$2 && $1==$4
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pat LLP LLP adp SLP $1==$2 && $1==$4 && directadd($3)
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kills all_indir, DLOCAL %bd==$1
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uses AA_REG = {DLOCAL, $1}
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gen add_l {const4, $3}, {DLOCAL, $1}
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killreg %a
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yields %a
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pat LLP adp SLP $1==$3 && inreg($1)==reg_pointer && abs_small($2)
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pat LLP LLP adp SLP $1==$2 && $1==$4 && directsub($3)
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kills all_indir, DLOCAL %bd==$1
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uses AA_REG = {DLOCAL, $1}
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gen sub_l {const4, 0-$3}, {DLOCAL, $1}
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killreg %a
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yields %a
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pat LLP LLP adp SLP $1==$2 && $1==$4
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kills all_indir, DLOCAL %bd==$1
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uses AA_REG = {DLOCAL, $1}, DD_REG4 = {const4, $3}
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gen add_l %b, {DLOCAL, $1}
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killreg %a
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yields %a
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pat LLP adp SLP $1==$3 && inreg($1)==reg_pointer && directadd($2)
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kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
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gen add_l {const4, $2}, {DLOCAL, $1}
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pat LLP adp SLP $1==$3 && inreg($1)==reg_pointer && directsub($2)
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kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
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gen sub_l {const4, 0-$2}, {DLOCAL, $1}
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pat LLP adp SLP $1==$3 && inreg($1)==reg_pointer
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kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
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uses DD_REG4 = {const4, $2}
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gen add_l %a, {DLOCAL, $1}
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pat LLP adp SLP $1==$3 && abs_small($2)
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pat LLP adp SLP $1==$3 && directadd($2)
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kills all_indir, DLOCAL %bd==$1
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uses DD_REG4 = {const4, $2}
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gen add_l %a, {DLOCAL, $1}
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gen add_l {const4, $2}, {DLOCAL, $1}
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pat LLP adp SLP $1==$3 && directsub($2)
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kills all_indir, DLOCAL %bd==$1
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gen sub_l {const4, 0-$2}, {DLOCAL, $1}
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pat LLP adp SLP $1==$3
|
||||
kills all_indir, DLOCAL %bd==$1
|
||||
gen add_l {const4, $2}, {DLOCAL, $1}
|
||||
uses DD_REG4 = {const4, $2}
|
||||
gen add_l %a, {DLOCAL, $1}
|
||||
|
||||
#if WORD_SIZE!=2
|
||||
pat lil lil adp sil sti $1==$2 && $1==$4 && inreg($1)==reg_pointer && $5<=4
|
||||
|
|
|
|||
|
|
@ -29,7 +29,8 @@ Something very wrong here!
|
|||
*/
|
||||
|
||||
#define small(x) ((x)>=1 && (x)<=8)
|
||||
#define abs_small(x) ((x)>=0-8 && (x)<=8)
|
||||
#define directadd(x) (small(x) || (x)>128)
|
||||
#define directsub(x) (directadd(0-x))
|
||||
#define nicesize(x) ((x)==1||(x)==2||(x)==4||(x)==8)
|
||||
#define low8(x) ((x) & 0377)
|
||||
#define low16(x) ((x) & 0177777)
|
||||
|
|
@ -49,11 +50,11 @@ TIMEFACTOR = 1/2
|
|||
PROPERTIES
|
||||
|
||||
D_REG /* data registers */
|
||||
A_REG(EM_PSIZE) /* address registers */
|
||||
A_REG(4) /* address registers */
|
||||
DD_REG /* allocatable D_REG, may not be a register variable */
|
||||
AA_REG(EM_PSIZE) /* allocatable A_REG, may not be a register variable */
|
||||
AA_REG(4) /* allocatable A_REG, may not be a register variable */
|
||||
RD_REG /* data register, register var */
|
||||
RA_REG(EM_PSIZE) /* address register, register var */
|
||||
RA_REG(4) /* address register, register var */
|
||||
#if WORD_SIZE==2
|
||||
D_REG4(4) /* data register, 4 bytes */
|
||||
DD_REG4(4) /* allocatable D_REG, 4 bytes */
|
||||
|
|
@ -2603,31 +2604,31 @@ pat LLP sti LLP adp SLP $1==$3 && $1==$5 && $2==1 && $4==1 &&
|
|||
inreg($1)==reg_pointer
|
||||
with any1
|
||||
kills allexceptcon, regvar($1, reg_pointer)
|
||||
gen move_b %1, {post_inc1, regvar($1, reg_pointer)}
|
||||
gen move %1, {post_inc1, regvar($1, reg_pointer)}
|
||||
|
||||
/* Normally, LLP sti will ve optimzed into sil */
|
||||
pat LLP sti LLP adp SLP $1==$3 && $1==$5 && $2==2 && $4==2 &&
|
||||
inreg($1)==reg_pointer
|
||||
with any2
|
||||
kills allexceptcon, regvar($1, reg_pointer)
|
||||
gen move_w %1, {post_inc2, regvar($1, reg_pointer)}
|
||||
gen move %1, {post_inc2, regvar($1, reg_pointer)}
|
||||
|
||||
pat LLP sti LLP adp SLP $1==$3 && $1==$5 && $2==4 && $4==4 &&
|
||||
inreg($1)==reg_pointer
|
||||
with any4
|
||||
kills allexceptcon, regvar($1, reg_pointer)
|
||||
gen move_l %1, {post_inc4, regvar($1, reg_pointer)}
|
||||
gen move %1, {post_inc4, regvar($1, reg_pointer)}
|
||||
|
||||
pat LLP LLP adp SLP sti $1==$2 && $1==$4 && $3==WORD_SIZE && $5==WORD_SIZE &&
|
||||
inreg($1)==reg_pointer
|
||||
with any_int-sconsts
|
||||
kills allexceptcon, regvar($1, reg_pointer)
|
||||
gen move_i %1, {post_inc_int, regvar($1, reg_pointer)}
|
||||
gen move %1, {post_inc_int, regvar($1, reg_pointer)}
|
||||
|
||||
pat sil LLP adp SLP $1==$2 && $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer
|
||||
with any_int-sconsts
|
||||
kills allexceptcon, regvar($1, reg_pointer)
|
||||
gen move_i %1, {post_inc_int, regvar($1, reg_pointer)}
|
||||
gen move %1, {post_inc_int, regvar($1, reg_pointer)}
|
||||
|
||||
pat LLP adp SLP LLP loi $1==$3 && $1==$4 && $2==0-1 && $5==1 &&
|
||||
inreg($1)==reg_pointer
|
||||
|
|
@ -2654,35 +2655,42 @@ pat LLP adp SLP LLP sti $1==$3 && $1==$4 && $2==0-1 && $5==1 &&
|
|||
inreg($1)==reg_pointer
|
||||
with any1
|
||||
kills allexceptcon, regvar($1, reg_pointer)
|
||||
gen move_b %1, {pre_dec1, regvar($1, reg_pointer)}
|
||||
gen move %1, {pre_dec1, regvar($1, reg_pointer)}
|
||||
|
||||
#if WORD_SIZE!=2
|
||||
pat LLP adp SLP LLP sti $1==$3 && $1==$4 && $2==0-2 && $5==2 &&
|
||||
inreg($1)==reg_pointer
|
||||
with any2
|
||||
kills allexceptcon, regvar($1, reg_pointer)
|
||||
gen move_w %1, {pre_dec2, regvar($1, reg_pointer)}
|
||||
gen move %1, {pre_dec2, regvar($1, reg_pointer)}
|
||||
#else
|
||||
pat LLP adp SLP LLP sti $1==$3 && $1==$4 && $2==0-4 && $5==4 &&
|
||||
inreg($1)==reg_pointer
|
||||
with any4
|
||||
kills allexceptcon, regvar($1, reg_pointer)
|
||||
gen move_l %1, {pre_dec4, regvar($1, reg_pointer)}
|
||||
gen move %1, {pre_dec4, regvar($1, reg_pointer)}
|
||||
#endif
|
||||
|
||||
pat LLP adp SLP sil $1==$3 && $1==$4 && $2==0-WORD_SIZE &&
|
||||
inreg($1)==reg_pointer
|
||||
with any_int-sconsts
|
||||
kills allexceptcon, regvar($1, reg_pointer)
|
||||
gen move_i %1, {pre_dec_int, regvar($1, reg_pointer)}
|
||||
gen move %1, {pre_dec_int, regvar($1, reg_pointer)}
|
||||
|
||||
pat LLP LLP adp SLP $1==$2 && $1==$4 && inreg($1)==reg_pointer && abs_small($3)
|
||||
pat LLP LLP adp SLP $1==$2 && $1==$4 && inreg($1)==reg_pointer && directadd($3)
|
||||
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
|
||||
uses AA_REG = {DLOCAL, $1}
|
||||
gen add_l {const4, $3}, {DLOCAL, $1}
|
||||
killreg %a
|
||||
yields %a
|
||||
|
||||
pat LLP LLP adp SLP $1==$2 && $1==$4 && inreg($1)==reg_pointer && directsub($3)
|
||||
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
|
||||
uses AA_REG = {DLOCAL, $1}
|
||||
gen sub_l {const4, 0-$3}, {DLOCAL, $1}
|
||||
killreg %a
|
||||
yields %a
|
||||
|
||||
pat LLP LLP adp SLP $1==$2 && $1==$4 && inreg($1)==reg_pointer
|
||||
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
|
||||
uses AA_REG = {DLOCAL, $1}, DD_REG4 = {const4, $3}
|
||||
|
|
@ -2690,37 +2698,52 @@ pat LLP LLP adp SLP $1==$2 && $1==$4 && inreg($1)==reg_pointer
|
|||
killreg %a
|
||||
yields %a
|
||||
|
||||
pat LLP LLP adp SLP $1==$2 && $1==$4 && abs_small($3)
|
||||
kills all_indir, DLOCAL %bd==$1
|
||||
uses AA_REG = {DLOCAL, $1}, DD_REG4 = {const4, $3}
|
||||
gen add_l %b, {DLOCAL, $1}
|
||||
killreg %a
|
||||
yields %a
|
||||
|
||||
pat LLP LLP adp SLP $1==$2 && $1==$4
|
||||
pat LLP LLP adp SLP $1==$2 && $1==$4 && directadd($3)
|
||||
kills all_indir, DLOCAL %bd==$1
|
||||
uses AA_REG = {DLOCAL, $1}
|
||||
gen add_l {const4, $3}, {DLOCAL, $1}
|
||||
killreg %a
|
||||
yields %a
|
||||
|
||||
pat LLP adp SLP $1==$3 && inreg($1)==reg_pointer && abs_small($2)
|
||||
pat LLP LLP adp SLP $1==$2 && $1==$4 && directsub($3)
|
||||
kills all_indir, DLOCAL %bd==$1
|
||||
uses AA_REG = {DLOCAL, $1}
|
||||
gen sub_l {const4, 0-$3}, {DLOCAL, $1}
|
||||
killreg %a
|
||||
yields %a
|
||||
|
||||
pat LLP LLP adp SLP $1==$2 && $1==$4
|
||||
kills all_indir, DLOCAL %bd==$1
|
||||
uses AA_REG = {DLOCAL, $1}, DD_REG4 = {const4, $3}
|
||||
gen add_l %b, {DLOCAL, $1}
|
||||
killreg %a
|
||||
yields %a
|
||||
|
||||
pat LLP adp SLP $1==$3 && inreg($1)==reg_pointer && directadd($2)
|
||||
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
|
||||
gen add_l {const4, $2}, {DLOCAL, $1}
|
||||
|
||||
pat LLP adp SLP $1==$3 && inreg($1)==reg_pointer && directsub($2)
|
||||
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
|
||||
gen sub_l {const4, 0-$2}, {DLOCAL, $1}
|
||||
|
||||
pat LLP adp SLP $1==$3 && inreg($1)==reg_pointer
|
||||
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
|
||||
uses DD_REG4 = {const4, $2}
|
||||
gen add_l %a, {DLOCAL, $1}
|
||||
|
||||
pat LLP adp SLP $1==$3 && abs_small($2)
|
||||
pat LLP adp SLP $1==$3 && directadd($2)
|
||||
kills all_indir, DLOCAL %bd==$1
|
||||
uses DD_REG4 = {const4, $2}
|
||||
gen add_l %a, {DLOCAL, $1}
|
||||
gen add_l {const4, $2}, {DLOCAL, $1}
|
||||
|
||||
pat LLP adp SLP $1==$3 && directsub($2)
|
||||
kills all_indir, DLOCAL %bd==$1
|
||||
gen sub_l {const4, 0-$2}, {DLOCAL, $1}
|
||||
|
||||
pat LLP adp SLP $1==$3
|
||||
kills all_indir, DLOCAL %bd==$1
|
||||
gen add_l {const4, $2}, {DLOCAL, $1}
|
||||
uses DD_REG4 = {const4, $2}
|
||||
gen add_l %a, {DLOCAL, $1}
|
||||
|
||||
#if WORD_SIZE!=2
|
||||
pat lil lil adp sil sti $1==$2 && $1==$4 && inreg($1)==reg_pointer && $5<=4
|
||||
|
|
|
|||
|
|
@ -29,7 +29,8 @@ Something very wrong here!
|
|||
*/
|
||||
|
||||
#define small(x) ((x)>=1 && (x)<=8)
|
||||
#define abs_small(x) ((x)>=0-8 && (x)<=8)
|
||||
#define directadd(x) (small(x) || (x)>128)
|
||||
#define directsub(x) (directadd(0-x))
|
||||
#define nicesize(x) ((x)==1||(x)==2||(x)==4||(x)==8)
|
||||
#define low8(x) ((x) & 0377)
|
||||
#define low16(x) ((x) & 0177777)
|
||||
|
|
@ -49,11 +50,11 @@ TIMEFACTOR = 1/2
|
|||
PROPERTIES
|
||||
|
||||
D_REG /* data registers */
|
||||
A_REG(EM_PSIZE) /* address registers */
|
||||
A_REG(4) /* address registers */
|
||||
DD_REG /* allocatable D_REG, may not be a register variable */
|
||||
AA_REG(EM_PSIZE) /* allocatable A_REG, may not be a register variable */
|
||||
AA_REG(4) /* allocatable A_REG, may not be a register variable */
|
||||
RD_REG /* data register, register var */
|
||||
RA_REG(EM_PSIZE) /* address register, register var */
|
||||
RA_REG(4) /* address register, register var */
|
||||
#if WORD_SIZE==2
|
||||
D_REG4(4) /* data register, 4 bytes */
|
||||
DD_REG4(4) /* allocatable D_REG, 4 bytes */
|
||||
|
|
@ -2603,31 +2604,31 @@ pat LLP sti LLP adp SLP $1==$3 && $1==$5 && $2==1 && $4==1 &&
|
|||
inreg($1)==reg_pointer
|
||||
with any1
|
||||
kills allexceptcon, regvar($1, reg_pointer)
|
||||
gen move_b %1, {post_inc1, regvar($1, reg_pointer)}
|
||||
gen move %1, {post_inc1, regvar($1, reg_pointer)}
|
||||
|
||||
/* Normally, LLP sti will ve optimzed into sil */
|
||||
pat LLP sti LLP adp SLP $1==$3 && $1==$5 && $2==2 && $4==2 &&
|
||||
inreg($1)==reg_pointer
|
||||
with any2
|
||||
kills allexceptcon, regvar($1, reg_pointer)
|
||||
gen move_w %1, {post_inc2, regvar($1, reg_pointer)}
|
||||
gen move %1, {post_inc2, regvar($1, reg_pointer)}
|
||||
|
||||
pat LLP sti LLP adp SLP $1==$3 && $1==$5 && $2==4 && $4==4 &&
|
||||
inreg($1)==reg_pointer
|
||||
with any4
|
||||
kills allexceptcon, regvar($1, reg_pointer)
|
||||
gen move_l %1, {post_inc4, regvar($1, reg_pointer)}
|
||||
gen move %1, {post_inc4, regvar($1, reg_pointer)}
|
||||
|
||||
pat LLP LLP adp SLP sti $1==$2 && $1==$4 && $3==WORD_SIZE && $5==WORD_SIZE &&
|
||||
inreg($1)==reg_pointer
|
||||
with any_int-sconsts
|
||||
kills allexceptcon, regvar($1, reg_pointer)
|
||||
gen move_i %1, {post_inc_int, regvar($1, reg_pointer)}
|
||||
gen move %1, {post_inc_int, regvar($1, reg_pointer)}
|
||||
|
||||
pat sil LLP adp SLP $1==$2 && $1==$4 && $3==WORD_SIZE && inreg($1)==reg_pointer
|
||||
with any_int-sconsts
|
||||
kills allexceptcon, regvar($1, reg_pointer)
|
||||
gen move_i %1, {post_inc_int, regvar($1, reg_pointer)}
|
||||
gen move %1, {post_inc_int, regvar($1, reg_pointer)}
|
||||
|
||||
pat LLP adp SLP LLP loi $1==$3 && $1==$4 && $2==0-1 && $5==1 &&
|
||||
inreg($1)==reg_pointer
|
||||
|
|
@ -2654,35 +2655,42 @@ pat LLP adp SLP LLP sti $1==$3 && $1==$4 && $2==0-1 && $5==1 &&
|
|||
inreg($1)==reg_pointer
|
||||
with any1
|
||||
kills allexceptcon, regvar($1, reg_pointer)
|
||||
gen move_b %1, {pre_dec1, regvar($1, reg_pointer)}
|
||||
gen move %1, {pre_dec1, regvar($1, reg_pointer)}
|
||||
|
||||
#if WORD_SIZE!=2
|
||||
pat LLP adp SLP LLP sti $1==$3 && $1==$4 && $2==0-2 && $5==2 &&
|
||||
inreg($1)==reg_pointer
|
||||
with any2
|
||||
kills allexceptcon, regvar($1, reg_pointer)
|
||||
gen move_w %1, {pre_dec2, regvar($1, reg_pointer)}
|
||||
gen move %1, {pre_dec2, regvar($1, reg_pointer)}
|
||||
#else
|
||||
pat LLP adp SLP LLP sti $1==$3 && $1==$4 && $2==0-4 && $5==4 &&
|
||||
inreg($1)==reg_pointer
|
||||
with any4
|
||||
kills allexceptcon, regvar($1, reg_pointer)
|
||||
gen move_l %1, {pre_dec4, regvar($1, reg_pointer)}
|
||||
gen move %1, {pre_dec4, regvar($1, reg_pointer)}
|
||||
#endif
|
||||
|
||||
pat LLP adp SLP sil $1==$3 && $1==$4 && $2==0-WORD_SIZE &&
|
||||
inreg($1)==reg_pointer
|
||||
with any_int-sconsts
|
||||
kills allexceptcon, regvar($1, reg_pointer)
|
||||
gen move_i %1, {pre_dec_int, regvar($1, reg_pointer)}
|
||||
gen move %1, {pre_dec_int, regvar($1, reg_pointer)}
|
||||
|
||||
pat LLP LLP adp SLP $1==$2 && $1==$4 && inreg($1)==reg_pointer && abs_small($3)
|
||||
pat LLP LLP adp SLP $1==$2 && $1==$4 && inreg($1)==reg_pointer && directadd($3)
|
||||
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
|
||||
uses AA_REG = {DLOCAL, $1}
|
||||
gen add_l {const4, $3}, {DLOCAL, $1}
|
||||
killreg %a
|
||||
yields %a
|
||||
|
||||
pat LLP LLP adp SLP $1==$2 && $1==$4 && inreg($1)==reg_pointer && directsub($3)
|
||||
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
|
||||
uses AA_REG = {DLOCAL, $1}
|
||||
gen sub_l {const4, 0-$3}, {DLOCAL, $1}
|
||||
killreg %a
|
||||
yields %a
|
||||
|
||||
pat LLP LLP adp SLP $1==$2 && $1==$4 && inreg($1)==reg_pointer
|
||||
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
|
||||
uses AA_REG = {DLOCAL, $1}, DD_REG4 = {const4, $3}
|
||||
|
|
@ -2690,37 +2698,52 @@ pat LLP LLP adp SLP $1==$2 && $1==$4 && inreg($1)==reg_pointer
|
|||
killreg %a
|
||||
yields %a
|
||||
|
||||
pat LLP LLP adp SLP $1==$2 && $1==$4 && abs_small($3)
|
||||
kills all_indir, DLOCAL %bd==$1
|
||||
uses AA_REG = {DLOCAL, $1}, DD_REG4 = {const4, $3}
|
||||
gen add_l %b, {DLOCAL, $1}
|
||||
killreg %a
|
||||
yields %a
|
||||
|
||||
pat LLP LLP adp SLP $1==$2 && $1==$4
|
||||
pat LLP LLP adp SLP $1==$2 && $1==$4 && directadd($3)
|
||||
kills all_indir, DLOCAL %bd==$1
|
||||
uses AA_REG = {DLOCAL, $1}
|
||||
gen add_l {const4, $3}, {DLOCAL, $1}
|
||||
killreg %a
|
||||
yields %a
|
||||
|
||||
pat LLP adp SLP $1==$3 && inreg($1)==reg_pointer && abs_small($2)
|
||||
pat LLP LLP adp SLP $1==$2 && $1==$4 && directsub($3)
|
||||
kills all_indir, DLOCAL %bd==$1
|
||||
uses AA_REG = {DLOCAL, $1}
|
||||
gen sub_l {const4, 0-$3}, {DLOCAL, $1}
|
||||
killreg %a
|
||||
yields %a
|
||||
|
||||
pat LLP LLP adp SLP $1==$2 && $1==$4
|
||||
kills all_indir, DLOCAL %bd==$1
|
||||
uses AA_REG = {DLOCAL, $1}, DD_REG4 = {const4, $3}
|
||||
gen add_l %b, {DLOCAL, $1}
|
||||
killreg %a
|
||||
yields %a
|
||||
|
||||
pat LLP adp SLP $1==$3 && inreg($1)==reg_pointer && directadd($2)
|
||||
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
|
||||
gen add_l {const4, $2}, {DLOCAL, $1}
|
||||
|
||||
pat LLP adp SLP $1==$3 && inreg($1)==reg_pointer && directsub($2)
|
||||
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
|
||||
gen sub_l {const4, 0-$2}, {DLOCAL, $1}
|
||||
|
||||
pat LLP adp SLP $1==$3 && inreg($1)==reg_pointer
|
||||
kills regvar($1, reg_pointer), all_regind %reg==regvar($1, reg_pointer)
|
||||
uses DD_REG4 = {const4, $2}
|
||||
gen add_l %a, {DLOCAL, $1}
|
||||
|
||||
pat LLP adp SLP $1==$3 && abs_small($2)
|
||||
pat LLP adp SLP $1==$3 && directadd($2)
|
||||
kills all_indir, DLOCAL %bd==$1
|
||||
uses DD_REG4 = {const4, $2}
|
||||
gen add_l %a, {DLOCAL, $1}
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gen add_l {const4, $2}, {DLOCAL, $1}
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pat LLP adp SLP $1==$3 && directsub($2)
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kills all_indir, DLOCAL %bd==$1
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gen sub_l {const4, 0-$2}, {DLOCAL, $1}
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pat LLP adp SLP $1==$3
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kills all_indir, DLOCAL %bd==$1
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gen add_l {const4, $2}, {DLOCAL, $1}
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uses DD_REG4 = {const4, $2}
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gen add_l %a, {DLOCAL, $1}
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#if WORD_SIZE!=2
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pat lil lil adp sil sti $1==$2 && $1==$4 && inreg($1)==reg_pointer && $5<=4
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|
|
|
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Loading…
Reference in a new issue