Some modifications to reduce the number of terminals (for Ultrix)
This commit is contained in:
ceriel
parent
8f661ca8a9
commit
df77506e1f
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@ -11,7 +11,6 @@
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%token <y_word> DREG
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%token <y_word> AREG
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%token <y_word> PC
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%token <y_word> ZPC
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%token <y_word> CREG
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%token <y_word> SPEC
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%token <y_word> ABCD
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@ -39,17 +38,15 @@
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%token <y_word> DIVL
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%token <y_word> CMP
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%token <y_word> MOVE
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%token <y_word> MOVEP
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%token <y_word> MOVEM
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%token <y_word> MOVEC
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%token <y_word> MOVES
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%token <y_word> MOVESP
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%token <y_word> SWAP
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%token <y_word> LINK
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%token <y_word> UNLK
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%token <y_word> TRAP
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%token <y_word> STOP
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%token <y_word> EXG
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%token <y_word> RTD
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%token <y_word> OP_IMM
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%token <y_word> BKPT
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%token <y_word> CALLM
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%token <y_word> CAS
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@ -58,8 +55,7 @@
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%token <y_word> CPBCC
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%token <y_word> CPDBCC
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%token <y_word> CPGEN
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%token <y_word> CPRESTORE
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%token <y_word> CPSAVE
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%token <y_word> CPSAVREST
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%token <y_word> CPSCC
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%token <y_word> CPTRAPCC
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%token <y_word> FPCR
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@ -31,7 +31,7 @@
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0, AREG, 07, "sp",
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0, PC, 0, "pc",
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0, ZPC, 0, "zpc",
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0, PC, 0200, "zpc",
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0, CREG, 04001, "vbr",
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0, CREG, 0, "sfc",
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@ -190,9 +190,9 @@
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0, CMP, 0, "cmp",
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0, MOVE, 0, "move",
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0, MOVEP, 0, "movep",
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0, MOVESP, 0, "movep",
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0, MOVEM, 0, "movem",
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0, MOVES, 0, "moves",
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0, MOVESP, 1, "moves",
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0, MOVEC, 0, "movec",
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0, SWAP, 0, "swap",
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@ -203,7 +203,7 @@
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0, TRAP, 0, "trap",
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0, STOP, 0, "stop",
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0, OP_IMM, 047162, "stop",
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0, CHK, 0, "chk",
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@ -213,7 +213,7 @@
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0, LEA, 0, "lea",
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0, RTD, 0, "rtd",
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0, OP_IMM, 047164, "rtd",
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0, BKPT, 0, "bkpt",
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@ -238,8 +238,8 @@
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0, CPTRAPCC, 0170170, ".trap",
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0, CPBCC, 0170200, ".br", /* 'r' to distinguish from SIZE_B
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*/
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0, CPSAVE, 0170400, ".save",
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0, CPRESTORE, 0170500, ".restore",
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0, CPSAVREST, 0170400, ".save",
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0, CPSAVREST, 0170500, ".restore",
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/* floating point coprocessor ... */
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@ -6,6 +6,10 @@
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/*
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* Motorola 68020 syntax rules
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*/
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/* Please do not add more terminal symbols. As it is, 127 terminal symbols
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are used, and this is the limit for some "yacc" implementations,
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notably the Ultrix one.
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*/
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operation
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: { instrp = instr;
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@ -123,14 +127,15 @@ instruction
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}
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| MOVE sizenon ea_ea
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{ move($2);}
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| MOVEP sizedef ea_ea
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{ movep($2);}
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| MOVEM sizedef regs ',' notimmreg
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{ movem(0, $2, $3);}
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| MOVEM sizedef notimmreg ',' regs
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{ movem(1, $2, $5);}
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| MOVES sizedef ea_ea
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{ if (mrg_1 <= 017) {
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| MOVESP sizedef ea_ea
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{ if ($1 == 0) {
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/* movep */
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movep($2);
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} else if (mrg_1 <= 017) {
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T_EMIT2(007000 | $2 | mrg_2,0,0,0);
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T_EMIT2(mrg_1 << 12 | 04000,0,0,0);
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ea_2($2,ALT|MEM);
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@ -165,8 +170,8 @@ instruction
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}
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| SWAP DREG
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{ T_EMIT2(044100 | $2,0,0,0);}
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| STOP imm
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{ T_EMIT2(047162, 0, 0, 0);
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| OP_IMM imm
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{ T_EMIT2($1, 0, 0, 0);
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ea_2(SIZE_W, 0);
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}
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| LINK sizenon AREG ',' imm
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@ -177,10 +182,6 @@ instruction
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{ fit(fit4($3));
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T_EMIT2(047100|low4($3),0,0,0);
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}
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| RTD imm
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{ T_EMIT2(047164,0,0,0);
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ea_2(SIZE_W, 0);
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}
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| BKPT '#' absexp
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{ fit(($3 & ~07) == 0);
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T_EMIT2(044110 | low3($3),0,0,0);
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@ -335,9 +336,9 @@ areg_index
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}
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;
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areg : AREG
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| PC { mrg_2 |= PC_MODE;}
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| ZPC { mrg_2 |= PC_MODE;
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ffew_2 |= 0200; /* base-reg suppressed */
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| PC { mrg_2 |= PC_MODE;
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ffew_2 |= $1; /* base-reg suppressed for zpc */
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$$ = 0;
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}
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;
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index : reg sizedef scale
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@ -633,13 +634,13 @@ mm_op1 : /* Coprocessor instructions; syntax may be changed (please).
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* NO EFFECTIVE ADDRESS IS CALCULATED (SYNTAX ?)
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*/
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}
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| CPRESTORE ea
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| CPSAVREST ea
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{ T_EMIT2($1 | co_id | mrg_2,0,0,0);
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ea_2(SIZE_W, (mrg_2 & 070)==030 ? 0 : CTR);
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}
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| CPSAVE ea
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{ T_EMIT2($1 | co_id | mrg_2,0,0,0);
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ea_2(SIZE_W,(mrg_2 & 070)==020 ? 0 : CTR|ALT);
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if ($1 & 0100) {
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/* restore */
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ea_2(SIZE_W, (mrg_2 & 070)==030 ? 0 : CTR);
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}
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else ea_2(SIZE_W,(mrg_2 & 070)==020 ? 0 : CTR|ALT);
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}
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| CPSCC cp_cond ea
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{ T_EMIT2($1 | co_id | mrg_2,0,0,0);
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@ -657,7 +658,7 @@ mm_op1 : /* Coprocessor instructions; syntax may be changed (please).
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T_EMIT2($2,0,0,0);
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}
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;
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cp_cond : '.' absexp
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cp_cond : DOT absexp
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{ fit(fit6($2));
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$$ = low6($2);
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}
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@ -14,6 +14,8 @@
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#undef valu_t
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#define valu_t long
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#undef word_t
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#define word_t long
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#undef addr_t
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#define addr_t long
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@ -24,13 +24,18 @@
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Bx - branch, size of offset determined by instruction
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Be - extended conditional branch; the instruction may be replaced
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by a reverse-conditional branch over a branch or jump
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To reduce the number of terminals, some instructions that have operands of
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equal size are coded with an X instead of b, w, or l; these instructions
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have the size in the high order word of the valu field. This is needed
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because some yacc versions do not accept grammars with more than 127
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terminal symbols.
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*/
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%token <y_word> REG
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%token <y_word> CASE_b_b_b, CASE_l_l_l, CASE_w_w_w
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%token <y_word> CASE_X_X_X
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%token <y_word> OP0
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%token <y_word> OP1_A, OP1_Bb, OP1_Bl, OP1_Bw, OP1_Bx, OP1_b, OP1_l, OP1_u,
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OP1_w, OP1_Be
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%token <y_word> OP1_A, OP1_Bx, OP1_u, OP1_Be
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%token <y_word> OP1_BX, OP1_X
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%token <y_word> OP2_A_A, OP2_A_l, OP2_b_b, OP2_b_l, OP2_b_u, OP2_b_w, OP2_l_A,
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OP2_l_Bb, OP2_l_b, OP2_l_l, OP2_l_u, OP2_l_w, OP2_u_b, OP2_u_l,
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OP2_u_u, OP2_u_w, OP2_w_b, OP2_w_l, OP2_w_u, OP2_w_w, OP2_l_Be
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@ -65,9 +65,9 @@
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0, OP2_b_b, 0x93, "bitb",
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0, OP2_w_w, 0xb3, "bitw",
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0, OP2_l_l, 0xd3, "bitl",
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0, OP1_b, 0x94, "clrb",
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0, OP1_w, 0xb4, "clrw",
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0, OP1_l, 0xd4, "clrl",
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0, OP1_X, 0x94|(1L<<16), "clrb",
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0, OP1_X, 0xb4|(2L<<16), "clrw",
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0, OP1_X, 0xd4|(4L<<16), "clrl",
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0, OP1_u, 0x7c, "clrq",
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0, OP1_u, 0x7cfd, "clro",
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0, OP2_b_b, 0x91, "cmpb",
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@ -79,9 +79,9 @@
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0, OP2_w_l, 0x32, "cvtwl",
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0, OP2_l_b, 0xf6, "cvtlb",
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0, OP2_l_w, 0xf7, "cvtlw",
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0, OP1_b, 0x97, "decb",
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0, OP1_w, 0xb7, "decw",
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0, OP1_l, 0xd7, "decl",
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0, OP1_X, 0x97|(1L<<16), "decb",
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0, OP1_X, 0xb7|(2L<<16), "decw",
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0, OP1_X, 0xd7|(4L<<16), "decl",
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0, OP2_b_b, 0x86, "divb2",
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0, OP3_b_b_b, 0x87, "divb3",
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0, OP2_w_w, 0xa6, "divw2",
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@ -90,9 +90,9 @@
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0, OP3_l_l_l, 0xc7, "divl3",
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0, OP4_l_u_l_l, 0x7b, "ediv",
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0, OP4_l_l_l_u, 0x7a, "emul",
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0, OP1_b, 0x96, "incb",
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0, OP1_w, 0xb6, "incw",
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0, OP1_l, 0xd6, "incl",
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0, OP1_X, 0x96|(1L<<16), "incb",
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0, OP1_X, 0xb6|(2L<<16), "incw",
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0, OP1_X, 0xd6|(4L<<16), "incl",
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0, OP2_b_b, 0x92, "mcomb",
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0, OP2_w_w, 0xb2, "mcomw",
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0, OP2_l_l, 0xd2, "mcoml",
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@ -113,7 +113,7 @@
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0, OP3_w_w_w, 0xa5, "mulw3",
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0, OP2_l_l, 0xc4, "mull2",
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0, OP3_l_l_l, 0xc5, "mull3",
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0, OP1_l, 0xdd, "pushl",
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0, OP1_X, 0xdd|(4L<<16), "pushl",
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0, OP3_b_l_l, 0x9c, "rotl",
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0, OP2_l_l, 0xd9, "sbwc",
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0, OP2_b_b, 0x82, "subb2",
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@ -122,9 +122,9 @@
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0, OP3_w_w_w, 0xa3, "subw3",
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0, OP2_l_l, 0xc2, "subl2",
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0, OP3_l_l_l, 0xc3, "subl3",
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0, OP1_b, 0x95, "tstb",
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0, OP1_w, 0xb5, "tstw",
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0, OP1_l, 0xd5, "tstl",
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0, OP1_X, 0x95|(1L<<16), "tstb",
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0, OP1_X, 0xb5|(2L<<16), "tstw",
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0, OP1_X, 0xd5|(4L<<16), "tstl",
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0, OP2_b_b, 0x8c, "xorb2",
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0, OP3_b_b_b, 0x8d, "xorb3",
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0, OP2_w_w, 0xac, "xorw2",
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@ -174,22 +174,22 @@
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0, OP4_u_u_u_Bw, 0x6ffd, "acbh",
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0, OP3_l_l_Bb, 0xf3, "aobleq",
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0, OP3_l_l_Bb, 0xf2, "aoblss",
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0, OP1_Bb, 0x14, "bgtr",
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0, OP1_Bb, 0x15, "bleq",
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0, OP1_Bb, 0x12, "bneq",
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0, OP1_Bb, 0x12, "bnequ",
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0, OP1_Bb, 0x13, "beql",
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0, OP1_Bb, 0x13, "beqlu",
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0, OP1_Bb, 0x18, "bgeq",
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0, OP1_Bb, 0x19, "blss",
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0, OP1_Bb, 0x1a, "bgtru",
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0, OP1_Bb, 0x1b, "blequ",
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0, OP1_Bb, 0x1c, "bvc",
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0, OP1_Bb, 0x1d, "bvs",
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0, OP1_Bb, 0x1e, "bgequ",
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0, OP1_Bb, 0x1e, "bcc",
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0, OP1_Bb, 0x1f, "blssu",
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0, OP1_Bb, 0x1f, "bcs",
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0, OP1_BX, 0x14|(1L<<16), "bgtr",
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0, OP1_BX, 0x15|(1L<<16), "bleq",
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0, OP1_BX, 0x12|(1L<<16), "bneq",
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0, OP1_BX, 0x12|(1L<<16), "bnequ",
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0, OP1_BX, 0x13|(1L<<16), "beql",
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0, OP1_BX, 0x13|(1L<<16), "beqlu",
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0, OP1_BX, 0x18|(1L<<16), "bgeq",
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0, OP1_BX, 0x19|(1L<<16), "blss",
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0, OP1_BX, 0x1a|(1L<<16), "bgtru",
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0, OP1_BX, 0x1b|(1L<<16), "blequ",
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0, OP1_BX, 0x1c|(1L<<16), "bvc",
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0, OP1_BX, 0x1d|(1L<<16), "bvs",
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0, OP1_BX, 0x1e|(1L<<16), "bgequ",
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0, OP1_BX, 0x1e|(1L<<16), "bcc",
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0, OP1_BX, 0x1f|(1L<<16), "blssu",
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0, OP1_BX, 0x1f|(1L<<16), "bcs",
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0, OP3_l_V_Bb, 0xe0, "bbs",
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0, OP3_l_V_Bb, 0xe1, "bbc",
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0, OP3_l_V_Bb, 0xe2, "bbss",
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@ -227,15 +227,15 @@
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0, OP3_l_V_Be, 0xe6, "jbssi",
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0, OP3_l_V_Be, 0xe7, "jbcci",
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0, OP1_Bx, 0x11, "br",
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0, OP1_Bb, 0x11, "brb",
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0, OP1_Bw, 0x31, "brw",
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0, OP1_BX, 0x11|(1L<<16), "brb",
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0, OP1_BX, 0x31|(2L<<16), "brw",
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0, OP1_Be, 0x11, "jbr",
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0, OP1_Bx, 0x10, "bsb",
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0, OP1_Bb, 0x10, "bsbb",
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0, OP1_Bw, 0x30, "bsbw",
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0, CASE_b_b_b, 0x8f, "caseb",
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0, CASE_w_w_w, 0xaf, "casew",
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0, CASE_l_l_l, 0xcf, "casel",
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0, OP1_BX, 0x10|(1L<<16), "bsbb",
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0, OP1_BX, 0x30|(2L<<16), "bsbw",
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0, CASE_X_X_X, 0x8f|(1L<<16), "caseb",
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0, CASE_X_X_X, 0xaf|(2L<<16), "casew",
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0, CASE_X_X_X, 0xcf|(4L<<16), "casel",
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0, OP1_A, 0x17, "jmp",
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0, OP1_A, 0x16, "jsb",
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0, OP0, 0x05, "rsb",
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@ -250,15 +250,15 @@
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/* Miscellaneous instructions */
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0, OP1_w, 0xb9, "bicpsw",
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0, OP1_w, 0xb8, "bispsw",
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0, OP1_X, 0xb9|(2L<<16), "bicpsw",
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0, OP1_X, 0xb8|(2L<<16), "bispsw",
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0, OP0, 0x03, "bpt",
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0, OP0, 0x00, "halt",
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0, OP6_l_l_l_l_l_l,0x0a, "index",
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0, OP1_l, 0xdc, "movpsl",
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0, OP1_X, 0xdc|(4L<<16), "movpsl",
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0, OP0, 0x01, "nop",
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0, OP1_w, 0xba, "popr",
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0, OP1_w, 0xbb, "pushr",
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0, OP1_X, 0xba|(2L<<16), "popr",
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0, OP1_X, 0xbb|(2L<<16), "pushr",
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0, OP0, 0xfc, "xfc",
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/* Queue instructions */
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|
@ -419,17 +419,17 @@
|
|||
to the VAX-11 Architecture Reference Manual, Revision 6.1, 1982, the
|
||||
access type is b, which means that the operand is a branch displacement.
|
||||
*/
|
||||
0, OP1_Bw, 0xfeff, "bugw",
|
||||
0, OP1_Bl, 0xfdff, "bugl",
|
||||
0, OP1_BX, 0xfeff|(2L<<16),"bugw",
|
||||
0, OP1_BX, 0xfdff|(4L<<16),"bugl",
|
||||
|
||||
0, OP3_b_w_A, 0x0c, "prober",
|
||||
0, OP3_b_w_A, 0x0d, "probew",
|
||||
|
||||
0, OP0, 0x02, "rei",
|
||||
0, OP1_w, 0xbc, "chmk",
|
||||
0, OP1_w, 0xbd, "chme",
|
||||
0, OP1_w, 0xbe, "chms",
|
||||
0, OP1_w, 0xbf, "chmu",
|
||||
0, OP1_X, 0xbc|(2L<<16), "chmk",
|
||||
0, OP1_X, 0xbd|(2L<<16), "chme",
|
||||
0, OP1_X, 0xbe|(2L<<16), "chms",
|
||||
0, OP1_X, 0xbf|(2L<<16), "chmu",
|
||||
|
||||
0, OP0, 0x06, "ldpctx",
|
||||
0, OP0, 0x07, "svpctx",
|
||||
|
|
|
|||
|
|
@ -36,17 +36,13 @@ operation
|
|||
;
|
||||
|
||||
OP1_O
|
||||
: OP1_b { opnd[0].size = 1; $$ = $1; }
|
||||
| OP1_w { opnd[0].size = 2; $$ = $1; }
|
||||
| OP1_l { opnd[0].size = 4; $$ = $1; }
|
||||
: OP1_X { opnd[0].size = $1>>16; $$ = $1 & 0xffff; }
|
||||
| OP1_A { opnd[0].size = -2; $$ = $1; }
|
||||
| OP1_u { opnd[0].size = 0; $$ = $1; }
|
||||
;
|
||||
|
||||
OP1_B
|
||||
: OP1_Bb { opnd[0].size = 1; $$ = $1; }
|
||||
| OP1_Bw { opnd[0].size = 2; $$ = $1; }
|
||||
| OP1_Bl { opnd[0].size = 4; $$ = $1; }
|
||||
: OP1_BX { opnd[0].size = $1>>16; $$ = $1 & 0xffff; }
|
||||
;
|
||||
|
||||
OP2_O_O
|
||||
|
|
@ -217,14 +213,10 @@ OP6_O_O_O_O_O_O
|
|||
;
|
||||
|
||||
CASE_O_O_O
|
||||
: CASE_b_b_b { opnd[0].size = 1; opnd[1].size = 1;
|
||||
opnd[2].size = 1; $$ = $1;
|
||||
}
|
||||
| CASE_w_w_w { opnd[0].size = 2; opnd[1].size = 2;
|
||||
opnd[2].size = 2; $$ = $1;
|
||||
}
|
||||
| CASE_l_l_l { opnd[0].size = 4; opnd[1].size = 4;
|
||||
opnd[2].size = 4; $$ = $1;
|
||||
: CASE_X_X_X { opnd[0].size = ($1>>16);
|
||||
opnd[1].size = ($1>>16);
|
||||
opnd[2].size = ($1>>16);
|
||||
$$ = $1 & 0xffff;
|
||||
}
|
||||
;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue