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shifts do NOT set condition codes properly

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ceriel 1992-12-14 16:40:22 +00:00
parent bc2744ca5c
commit e09aac1b4a
1 changed files with 8 additions and 8 deletions
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16
mach/i86/ncg/table
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@ -238,17 +238,17 @@ or rm:rw:cc, regorconst:ro.
or anyreg:rw:cc, rmorconst:ro. or anyreg:rw:cc, rmorconst:ro.
pop rmorconst:wo cost(1,8). pop rmorconst:wo cost(1,8).
push rmorconst:ro cost(1,10). push rmorconst:ro cost(1,10).
rcl rm:rw:cc, ANYCON+SHIFT_CREG:ro. rcl rm:rw, ANYCON+SHIFT_CREG:ro kills:cc.
rcr rm:rw:cc, ANYCON+SHIFT_CREG:ro. rcr rm:rw, ANYCON+SHIFT_CREG:ro kills:cc.
ret cost(1,8). ret cost(1,8).
rol rm:rw:cc, ANYCON+SHIFT_CREG:ro. rol rm:rw, ANYCON+SHIFT_CREG:ro kills:cc.
ror rm:rw:cc, ANYCON+SHIFT_CREG:ro. ror rm:rw, ANYCON+SHIFT_CREG:ro kills:cc.
sal rm:rw:cc, ANYCON+SHIFT_CREG:ro. sal rm:rw, ANYCON+SHIFT_CREG:ro kills:cc.
sar rm:rw:cc, ANYCON+SHIFT_CREG:ro. sar rm:rw, ANYCON+SHIFT_CREG:ro kills:cc.
sbb rm:rw:cc, regorconst:ro. sbb rm:rw:cc, regorconst:ro.
sbb anyreg:rw:cc, rmorconst:ro. sbb anyreg:rw:cc, rmorconst:ro.
shl rm:rw:cc, ANYCON+SHIFT_CREG:ro. shl rm:rw, ANYCON+SHIFT_CREG:ro kills:cc.
shr rm:rw:cc, ANYCON+SHIFT_CREG:ro. shr rm:rw, ANYCON+SHIFT_CREG:ro kills:cc.
sxx rm:rw:cc, ANYCON+SHIFT_CREG:ro. sxx rm:rw:cc, ANYCON+SHIFT_CREG:ro.
#ifdef REGVARS #ifdef REGVARS
sub LOCAL:rw:cc, rmorconst:ro. /* only for register variables; UNSAFE !!! */ sub LOCAL:rw:cc, rmorconst:ro. /* only for register variables; UNSAFE !!! */