Add "kills MEMORY" to powerpc sti rules.
Adjust some of the loi rules (and associated moves) so we can identify
the tokens that must be in MEMORY.
With this commit, I can navigate the Enterprise even if I comment out
my work-around from e22c888.
			
			
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					 1 changed files with 86 additions and 53 deletions
				
			
		|  | @ -214,8 +214,11 @@ TOKENS | ||||||
| 	SEX_H              = { GPR reg; }             4. | 	SEX_H              = { GPR reg; }             4. | ||||||
| 	 | 	 | ||||||
| 	IND_RC_B           = { GPR reg; INT off; }    4. | 	IND_RC_B           = { GPR reg; INT off; }    4. | ||||||
|  | 	IND_RR_B           = { GPR reg1; GPR reg2; }  4. | ||||||
| 	IND_RC_H           = { GPR reg; INT off; }    4. | 	IND_RC_H           = { GPR reg; INT off; }    4. | ||||||
|  | 	IND_RR_H           = { GPR reg1; GPR reg2; }  4. | ||||||
| 	IND_RC_H_S         = { GPR reg; INT off; }    4. | 	IND_RC_H_S         = { GPR reg; INT off; }    4. | ||||||
|  | 	IND_RR_H_S         = { GPR reg1; GPR reg2; }  4. | ||||||
| 	IND_RC_W           = { GPR reg; INT off; }    4. | 	IND_RC_W           = { GPR reg; INT off; }    4. | ||||||
| 	IND_RR_W           = { GPR reg1; GPR reg2; }  4. | 	IND_RR_W           = { GPR reg1; GPR reg2; }  4. | ||||||
| 	IND_RC_D           = { GPR reg; INT off; }    8. | 	IND_RC_D           = { GPR reg; INT off; }    8. | ||||||
|  | @ -254,9 +257,16 @@ SETS | ||||||
| 	LOGICAL_ALL        = NOT_R + AND_RR + OR_RR + OR_RC + XOR_RR + | 	LOGICAL_ALL        = NOT_R + AND_RR + OR_RR + OR_RC + XOR_RR + | ||||||
| 	                     XOR_RC. | 	                     XOR_RC. | ||||||
| 
 | 
 | ||||||
|  | 	/* indirect 4-byte value */ | ||||||
| 	IND_ALL_W          = IND_RC_W + IND_RR_W. | 	IND_ALL_W          = IND_RC_W + IND_RR_W. | ||||||
| 
 | 	/* indirect 8-byte value */ | ||||||
| 	IND_ALL_D          = IND_RC_D + IND_RR_D. | 	IND_ALL_D          = IND_RC_D + IND_RR_D. | ||||||
|  | 	/* any indirect value that fits in a GPR */ | ||||||
|  | 	IND_ALL_BHW        = IND_RC_B + IND_RR_B + IND_RC_H + IND_RR_H + | ||||||
|  | 	                     IND_RC_H_S + IND_RR_H_S + IND_ALL_W. | ||||||
|  | 
 | ||||||
|  | 	/* anything killed by sti (store indirect) */ | ||||||
|  | 	MEMORY             = IND_ALL_BHW + IND_ALL_D. | ||||||
| 
 | 
 | ||||||
| 	OP_ALL_W           = SUM_ALL + TRISTATE_ALL + SEX_ALL + LOGICAL_ALL + | 	OP_ALL_W           = SUM_ALL + TRISTATE_ALL + SEX_ALL + LOGICAL_ALL + | ||||||
| 	                     IND_ALL_W. | 	                     IND_ALL_W. | ||||||
|  | @ -301,18 +311,18 @@ INSTRUCTIONS | ||||||
|   fsubs           FSREG:wo, FSREG:ro, FSREG:ro. |   fsubs           FSREG:wo, FSREG:ro, FSREG:ro. | ||||||
|   fmr             FPR:wo, FPR:ro. |   fmr             FPR:wo, FPR:ro. | ||||||
|   fmr             FSREG:wo, FSREG:ro. |   fmr             FSREG:wo, FSREG:ro. | ||||||
|   lbzx            GPR:wo, GPR:ro, GPR:ro. |  | ||||||
|   lbz             GPR:wo, GPRINDIRECT:ro. |   lbz             GPR:wo, GPRINDIRECT:ro. | ||||||
|  |   lbzx            GPR:wo, GPR:ro, GPR:ro. | ||||||
|   lfd             FPR:wo, GPRINDIRECT:ro. |   lfd             FPR:wo, GPRINDIRECT:ro. | ||||||
|   lfdu            FPR:wo, GPRINDIRECT:ro. |   lfdu            FPR:wo, GPRINDIRECT:ro. | ||||||
|   lfdx            FPR:wo, GPR:ro, GPR:ro. |   lfdx            FPR:wo, GPR:ro, GPR:ro. | ||||||
|   lfs             FSREG:wo, GPRINDIRECT:ro. |   lfs             FSREG:wo, GPRINDIRECT:ro. | ||||||
|   lfsu            FSREG:wo, GPRINDIRECT:rw. |   lfsu            FSREG:wo, GPRINDIRECT:rw. | ||||||
|   lfsx            FSREG:wo, GPR:ro, GPR:ro. |   lfsx            FSREG:wo, GPR:ro, GPR:ro. | ||||||
|   lhzx            GPR:wo, GPR:ro, GPR:ro. |  | ||||||
|   lhax            GPR:wo, GPR:ro, GPR:ro. |  | ||||||
|   lha             GPR:wo, GPRINDIRECT:ro. |   lha             GPR:wo, GPRINDIRECT:ro. | ||||||
|  |   lhax            GPR:wo, GPR:ro, GPR:ro. | ||||||
|   lhz             GPR:wo, GPRINDIRECT:ro. |   lhz             GPR:wo, GPRINDIRECT:ro. | ||||||
|  |   lhzx            GPR:wo, GPR:ro, GPR:ro. | ||||||
|   li32            GPR:wo, LABEL:ro. |   li32            GPR:wo, LABEL:ro. | ||||||
|   lwzu            GPR:wo, GPRINDIRECT:ro. |   lwzu            GPR:wo, GPRINDIRECT:ro. | ||||||
|   lwzx            GPR:wo, GPR:ro, GPR:ro. |   lwzx            GPR:wo, GPR:ro, GPR:ro. | ||||||
|  | @ -420,35 +430,64 @@ MOVES | ||||||
| 			COMMENT("move SUM_RR->GPR") | 			COMMENT("move SUM_RR->GPR") | ||||||
| 			add %2, %1.reg1, %1.reg2 | 			add %2, %1.reg1, %1.reg2 | ||||||
| 
 | 
 | ||||||
| /* Read/write byte */ | /* Read byte */ | ||||||
| 
 | 
 | ||||||
| 	from IND_RC_B to GPR | 	from IND_RC_B to GPR | ||||||
| 		gen | 		gen | ||||||
| 			COMMENT("move IND_RC_B->GPR") | 			COMMENT("move IND_RC_B->GPR") | ||||||
| 			lbz %2, {GPRINDIRECT, %1.reg, %1.off} | 			lbz %2, {GPRINDIRECT, %1.reg, %1.off} | ||||||
| 
 | 
 | ||||||
|  | 	from IND_RR_B to GPR | ||||||
|  | 		gen | ||||||
|  | 			COMMENT("move IND_RR_B->GPR") | ||||||
|  | 			lbzx %2, %1.reg1, %1.reg2 | ||||||
|  | 
 | ||||||
|  | /* Write byte */ | ||||||
|  | 
 | ||||||
| 	from GPR to IND_RC_B | 	from GPR to IND_RC_B | ||||||
| 		gen | 		gen | ||||||
| 			COMMENT("move GPR->IND_RC_B") | 			COMMENT("move GPR->IND_RC_B") | ||||||
| 			stb %1, {GPRINDIRECT, %2.reg, %2.off} | 			stb %1, {GPRINDIRECT, %2.reg, %2.off} | ||||||
| 
 | 
 | ||||||
| /* Read/write halfword (short) */ | 	from GPR to IND_RR_B | ||||||
|  | 		gen | ||||||
|  | 			COMMENT("move GPR->IND_RR_B") | ||||||
|  | 			stbx %1, %2.reg1, %2.reg2 | ||||||
|  | 
 | ||||||
|  | /* Read halfword (short) */ | ||||||
| 
 | 
 | ||||||
| 	from IND_RC_H to GPR | 	from IND_RC_H to GPR | ||||||
| 		gen | 		gen | ||||||
| 			COMMENT("move IND_RC_H->GPR") | 			COMMENT("move IND_RC_H->GPR") | ||||||
| 			lhz %2, {GPRINDIRECT, %1.reg, %1.off} | 			lhz %2, {GPRINDIRECT, %1.reg, %1.off} | ||||||
| 
 | 
 | ||||||
|  | 	from IND_RR_H to GPR | ||||||
|  | 		gen | ||||||
|  | 			COMMENT("move IND_RR_H->GPR") | ||||||
|  | 			lhzx %2, %1.reg1, %1.reg2 | ||||||
|  | 
 | ||||||
| 	from IND_RC_H_S to GPR | 	from IND_RC_H_S to GPR | ||||||
| 		gen | 		gen | ||||||
| 			COMMENT("move IND_RC_H_S->GPR") | 			COMMENT("move IND_RC_H_S->GPR") | ||||||
| 			lha %2, {GPRINDIRECT, %1.reg, %1.off} | 			lha %2, {GPRINDIRECT, %1.reg, %1.off} | ||||||
| 
 | 
 | ||||||
|  | 	from IND_RR_H_S to GPR | ||||||
|  | 		gen | ||||||
|  | 			COMMENT("move IND_RR_H_S->GPR") | ||||||
|  | 			lhax %2, %1.reg1, %1.reg2 | ||||||
|  | 
 | ||||||
|  | /* Write halfword */ | ||||||
|  | 
 | ||||||
| 	from GPR to IND_RC_H | 	from GPR to IND_RC_H | ||||||
| 		gen | 		gen | ||||||
| 			COMMENT("move GPR->IND_RC_H") | 			COMMENT("move GPR->IND_RC_H") | ||||||
| 			sth %1, {GPRINDIRECT, %2.reg, %2.off} | 			sth %1, {GPRINDIRECT, %2.reg, %2.off} | ||||||
| 
 | 
 | ||||||
|  | 	from GPR to IND_RR_H | ||||||
|  | 		gen | ||||||
|  | 			COMMENT("move GPR->IND_RR_H") | ||||||
|  | 			sthx %1, %2.reg1, %2.reg2 | ||||||
|  | 
 | ||||||
| /* Read word */ | /* Read word */ | ||||||
| 
 | 
 | ||||||
| 	from IND_RC_W to GPR | 	from IND_RC_W to GPR | ||||||
|  | @ -670,7 +709,7 @@ STACKINGRULES | ||||||
| 			move %1, RSCRATCH | 			move %1, RSCRATCH | ||||||
| 			stwu RSCRATCH, {GPRINDIRECT, SP, 0-4} | 			stwu RSCRATCH, {GPRINDIRECT, SP, 0-4} | ||||||
| 			 | 			 | ||||||
| 	from IND_ALL_W to STACK | 	from IND_ALL_BHW to STACK | ||||||
| 		gen | 		gen | ||||||
| 			move %1, RSCRATCH | 			move %1, RSCRATCH | ||||||
| 			stwu RSCRATCH, {GPRINDIRECT, SP, 0-4} | 			stwu RSCRATCH, {GPRINDIRECT, SP, 0-4} | ||||||
|  | @ -771,7 +810,7 @@ COERCIONS | ||||||
| 			addi SP, SP, {CONST, 4} | 			addi SP, SP, {CONST, 4} | ||||||
| 		yields %a | 		yields %a | ||||||
| 		 | 		 | ||||||
| 	from IND_ALL_W | 	from IND_ALL_BHW | ||||||
| 		uses REG | 		uses REG | ||||||
| 		gen | 		gen | ||||||
| 			move %1, %a | 			move %1, %a | ||||||
|  | @ -1048,54 +1087,28 @@ PATTERNS | ||||||
| 
 | 
 | ||||||
| 	pat loi $1==INT8                   /* Load byte indirect */ | 	pat loi $1==INT8                   /* Load byte indirect */ | ||||||
| 		with GPR | 		with GPR | ||||||
| 			uses REG | 			yields {IND_RC_B, %1, 0} | ||||||
| 			gen |  | ||||||
| 				lbz %a, {GPRINDIRECT, %1, 0} |  | ||||||
| 			yields %a |  | ||||||
| 		with SUM_RR | 		with SUM_RR | ||||||
| 			uses reusing %1, REG | 			yields {IND_RR_B, %1.reg1, %1.reg2} | ||||||
| 			gen |  | ||||||
| 				lbzx %a, %1.reg1, %1.reg2 |  | ||||||
| 			yields %a |  | ||||||
| 		with SUM_RC | 		with SUM_RC | ||||||
| 			uses REG | 			yields {IND_RC_B, %1.reg, %1.off} | ||||||
| 			gen |  | ||||||
| 				move {IND_RC_B, %1.reg, %1.off}, %a |  | ||||||
| 			yields %a |  | ||||||
| 
 | 
 | ||||||
| 	pat loi loc loc cii $1==INT16 && $2==INT16 && $3==INT32 /* Load half-word indirect and sign extend */ | 	pat loi loc loc cii $1==INT16 && $2==INT16 && $3==INT32 | ||||||
|  | 	/* Load half-word indirect and sign extend */ | ||||||
| 		with GPR | 		with GPR | ||||||
| 			uses REG | 			yields {IND_RC_H_S, %1, 0} | ||||||
| 			gen |  | ||||||
| 				lha %a, {GPRINDIRECT, %1, 0} |  | ||||||
| 			yields %a |  | ||||||
| 		with SUM_RR | 		with SUM_RR | ||||||
| 			uses reusing %1, REG | 			yields {IND_RR_H_S, %1.reg1, %1.reg2} | ||||||
| 			gen |  | ||||||
| 				lhax %a, %1.reg1, %1.reg2 |  | ||||||
| 			yields %a |  | ||||||
| 		with SUM_RC | 		with SUM_RC | ||||||
| 			uses REG | 			yields {IND_RC_H_S, %1.reg, %1.off} | ||||||
| 			gen |  | ||||||
| 				move {IND_RC_H_S, %1.reg, %1.off}, %a |  | ||||||
| 			yields %a |  | ||||||
| 
 | 
 | ||||||
| 	pat loi $1==INT16                  /* Load half-word indirect */ | 	pat loi $1==INT16                  /* Load half-word indirect */ | ||||||
| 		with GPR | 		with GPR | ||||||
| 			uses REG | 			yields {IND_RC_H, %1, 0} | ||||||
| 			gen |  | ||||||
| 				lhz %a, {GPRINDIRECT, %1, 0} |  | ||||||
| 			yields %a |  | ||||||
| 		with SUM_RR | 		with SUM_RR | ||||||
| 			uses reusing %1, REG | 			yields {IND_RR_H, %1.reg1, %1.reg2} | ||||||
| 			gen |  | ||||||
| 				lhzx %a, %1.reg1, %1.reg2 |  | ||||||
| 			yields %a |  | ||||||
| 		with SUM_RC | 		with SUM_RC | ||||||
| 			uses REG | 			yields {IND_RC_H, %1.reg, %1.off} | ||||||
| 			gen |  | ||||||
| 				move {IND_RC_H, %1.reg, %1.off}, %a |  | ||||||
| 			yields %a |  | ||||||
| 
 | 
 | ||||||
| 	pat loi $1==INT32                  /* Load word indirect */ | 	pat loi $1==INT32                  /* Load word indirect */ | ||||||
| 		with GPR | 		with GPR | ||||||
|  | @ -1126,70 +1139,90 @@ PATTERNS | ||||||
| 
 | 
 | ||||||
| 	pat sti $1==INT8                   /* Store byte indirect */ | 	pat sti $1==INT8                   /* Store byte indirect */ | ||||||
| 		with GPR GPR | 		with GPR GPR | ||||||
|  | 			kills MEMORY | ||||||
| 			gen | 			gen | ||||||
| 				stb %2, {GPRINDIRECT, %1, 0} | 				stb %2, {GPRINDIRECT, %1, 0} | ||||||
| 		with SUM_RR GPR | 		with SUM_RR GPR | ||||||
|  | 			kills MEMORY | ||||||
| 			gen | 			gen | ||||||
| 				stbx %2, %1.reg1, %1.reg2 | 				stbx %2, %1.reg1, %1.reg2 | ||||||
| 		with SUM_RC GPR | 		with SUM_RC GPR | ||||||
|  | 			kills MEMORY | ||||||
| 			gen | 			gen | ||||||
| 				move %2, {IND_RC_B, %1.reg, %1.off} | 				move %2, {IND_RC_B, %1.reg, %1.off} | ||||||
| 		with GPR SEX_B | 		with GPR SEX_B | ||||||
|  | 			kills MEMORY | ||||||
| 			gen | 			gen | ||||||
| 				stb %2.reg, {GPRINDIRECT, %1, 0} | 				stb %2.reg, {GPRINDIRECT, %1, 0} | ||||||
| 		with SUM_RR SEX_B | 		with SUM_RR SEX_B | ||||||
|  | 			kills MEMORY | ||||||
| 			gen | 			gen | ||||||
| 				stbx %2.reg, %1.reg1, %1.reg2 | 				stbx %2.reg, %1.reg1, %1.reg2 | ||||||
| 		with SUM_RC SEX_B | 		with SUM_RC SEX_B | ||||||
|  | 			kills MEMORY | ||||||
| 			gen | 			gen | ||||||
| 				move %2.reg, {IND_RC_B, %1.reg, %1.off} | 				move %2.reg, {IND_RC_B, %1.reg, %1.off} | ||||||
| 
 | 
 | ||||||
| 	pat sti $1==INT16                  /* Store half-word indirect */ | 	pat sti $1==INT16                  /* Store half-word indirect */ | ||||||
| 		with GPR GPR | 		with GPR GPR | ||||||
|  | 			kills MEMORY | ||||||
| 			gen | 			gen | ||||||
| 				sth %2, {GPRINDIRECT, %1, 0} | 				sth %2, {GPRINDIRECT, %1, 0} | ||||||
| 		with SUM_RR GPR | 		with SUM_RR GPR | ||||||
|  | 			kills MEMORY | ||||||
| 			gen | 			gen | ||||||
| 				sthx %2, %1.reg1, %1.reg2 | 				sthx %2, %1.reg1, %1.reg2 | ||||||
| 		with SUM_RC GPR | 		with SUM_RC GPR | ||||||
|  | 			kills MEMORY | ||||||
| 			gen | 			gen | ||||||
| 				move %2, {IND_RC_H, %1.reg, %1.off} | 				move %2, {IND_RC_H, %1.reg, %1.off} | ||||||
| 		with GPR SEX_H | 		with GPR SEX_H | ||||||
|  | 			kills MEMORY | ||||||
| 			gen | 			gen | ||||||
| 				sth %2.reg, {GPRINDIRECT, %1, 0} | 				sth %2.reg, {GPRINDIRECT, %1, 0} | ||||||
| 		with SUM_RR SEX_H | 		with SUM_RR SEX_H | ||||||
|  | 			kills MEMORY | ||||||
| 			gen | 			gen | ||||||
| 				sthx %2.reg, %1.reg1, %1.reg2 | 				sthx %2.reg, %1.reg1, %1.reg2 | ||||||
| 		with SUM_RC SEX_H | 		with SUM_RC SEX_H | ||||||
|  | 			kills MEMORY | ||||||
| 			gen | 			gen | ||||||
| 				move %2.reg, {IND_RC_H, %1.reg, %1.off} | 				move %2.reg, {IND_RC_H, %1.reg, %1.off} | ||||||
| 
 | 
 | ||||||
| 	pat sti $1==INT32                  /* Store word indirect */ | 	pat sti $1==INT32                  /* Store word indirect */ | ||||||
| 		with GPR GPR+FSREG | 		with GPR GPR+FSREG | ||||||
|  | 			kills MEMORY | ||||||
| 			gen | 			gen | ||||||
| 				move %2, {IND_RC_W, %1, 0} | 				move %2, {IND_RC_W, %1, 0} | ||||||
| 		with SUM_RR GPR+FSREG | 		with SUM_RR GPR+FSREG | ||||||
|  | 			kills MEMORY | ||||||
| 			gen | 			gen | ||||||
| 				move %2, {IND_RR_W, %1.reg1, %1.reg2} | 				move %2, {IND_RR_W, %1.reg1, %1.reg2} | ||||||
| 		with SUM_RC GPR+FSREG | 		with SUM_RC GPR+FSREG | ||||||
|  | 			kills MEMORY | ||||||
| 			gen | 			gen | ||||||
| 				move %2, {IND_RC_W, %1.reg, %1.off} | 				move %2, {IND_RC_W, %1.reg, %1.off} | ||||||
| 
 | 
 | ||||||
| 	pat sti $1==INT64                  /* Store double-word indirect */ | 	pat sti $1==INT64                  /* Store double-word indirect */ | ||||||
| 		with GPR FREG | 		with GPR FREG | ||||||
|  | 			kills MEMORY | ||||||
| 			gen | 			gen | ||||||
| 				move %2, {IND_RC_D, %1, 0} | 				move %2, {IND_RC_D, %1, 0} | ||||||
| 		with SUM_RR FREG | 		with SUM_RR FREG | ||||||
|  | 			kills MEMORY | ||||||
| 			gen | 			gen | ||||||
| 				move %2, {IND_RR_D, %1.reg1, %1.reg2} | 				move %2, {IND_RR_D, %1.reg1, %1.reg2} | ||||||
| 		with SUM_RC FREG | 		with SUM_RC FREG | ||||||
|  | 			kills MEMORY | ||||||
| 			gen | 			gen | ||||||
| 				move %2, {IND_RC_D, %1.reg, %1.off} | 				move %2, {IND_RC_D, %1.reg, %1.off} | ||||||
| 		with GPR GPR GPR | 		with GPR GPR GPR | ||||||
|  | 			kills MEMORY | ||||||
| 			gen | 			gen | ||||||
| 				stw %2, {GPRINDIRECT, %1, 0} | 				stw %2, {GPRINDIRECT, %1, 0} | ||||||
| 				stw %3, {GPRINDIRECT, %1, 4} | 				stw %3, {GPRINDIRECT, %1, 4} | ||||||
| 		with SUM_RC GPR GPR | 		with SUM_RC GPR GPR | ||||||
|  | 			kills MEMORY | ||||||
| 			gen | 			gen | ||||||
| 				move %2, {IND_RC_W, %1.reg, %1.off} | 				move %2, {IND_RC_W, %1.reg, %1.off} | ||||||
| 				move %3, {IND_RC_W, %1.reg, %1.off+4} | 				move %3, {IND_RC_W, %1.reg, %1.off+4} | ||||||
|  | @ -1199,7 +1232,7 @@ PATTERNS | ||||||
| 			loc $1 | 			loc $1 | ||||||
| 			sts INT32 | 			sts INT32 | ||||||
| 
 | 
 | ||||||
| 	pat sts                            /* Load arbitrary size */ | 	pat sts                            /* Store arbitrary size */ | ||||||
| 		with GPR3 GPR4 STACK | 		with GPR3 GPR4 STACK | ||||||
| 			kills ALL | 			kills ALL | ||||||
| 			gen | 			gen | ||||||
|  |  | ||||||
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