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Add (largely untested) float/int conversion.

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--HG--
branch : dtrg-videocore
This commit is contained in:
David Given 2013-07-01 13:05:36 +01:00
parent 29af6f1adb
commit e36d739fa4
6 changed files with 50 additions and 25 deletions
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1
mach/vc4/as/mach1.c
View file

@ -25,3 +25,4 @@ extern void branch_addcmp_reg_lit_instr(int cc, int rd, int ra, long vs, struct
extern void branch_addcmp_lit_lit_instr(int cc, int rd, long va, long vs, struct expr_t* expr);
extern void lea_stack_instr(int rd, long va, int rs);
extern void lea_address_instr(int rd, struct expr_t* expr);
extern void fltcnv_instr(quad opcode, int cc, int rd, int ra, quad shift);

1
mach/vc4/as/mach2.c
View file

@ -17,6 +17,7 @@
%token <y_word> OP_MEM
%token <y_word> OP_MISC
%token <y_word> OP_MISCL
%token <y_word> OP_FLTCNV
%token <y_word> OP_STACK
%token <y_word> OP_LEA

5
mach/vc4/as/mach3.c
View file

@ -130,6 +130,11 @@
0, OP_MISC, B16(11001001,11100000), "exp2",
0, OP_MISC, B16(11000101,11100000), "adds256",
0, OP_FLTCNV, B16(11001010,00000000), "ftrunc",
0, OP_FLTCNV, B16(11001010,00100000), "floor",
0, OP_FLTCNV, B16(11001010,01000000), "flts",
0, OP_FLTCNV, B16(11001010,01100000), "fltu",
0, OP_MISCL, B16(11000100,10000000), "divs",
0, OP_MISCL, B16(11000100,11100000), "divu",

9
mach/vc4/as/mach4.c
View file

@ -74,5 +74,14 @@ operation
| OP_LEA GPR ',' absexp '(' GPR ')' { lea_stack_instr($2, $4, $6); }
| OP_LEA GPR ',' expr { lea_address_instr($2, &$4); }
| OP_FLTCNV GPR ',' GPR { fltcnv_instr($1, ALWAYS, $2, $4, 0); }
| OP_FLTCNV CC GPR ',' GPR { fltcnv_instr($1, $2, $3, $5, 0); }
| OP_FLTCNV GPR ',' GPR ',' shift '#' absexp { fltcnv_instr($1, ALWAYS, $2, $4, $8); }
| OP_FLTCNV CC GPR ',' GPR ',' shift '#' absexp { fltcnv_instr($1, $2, $3, $5, $9); }
;
shift
: 'l' 's' 'r'
| 'l' 's' 'l';

10
mach/vc4/as/mach5.c
View file

@ -487,3 +487,13 @@ void lea_address_instr(int rd, struct expr_t* expr)
emit4(expr->val - pc);
}
/* Floating point conversion opcodes (ftrunc, floor, flts, fltu). */
void fltcnv_instr(quad opcode, int cc, int rd, int ra, quad shift)
{
fitx(shift, 6);
emit2(opcode | (rd<<0));
emit2(B16(00000000,01000000) | (ra<<11) | (cc<<7) | shift);
}

47
mach/vc4/ncg/table
View file

@ -131,8 +131,11 @@ INSTRUCTIONS
fadd GPR:wo, GPR:ro, GPR:ro.
fcmp GPR:wo, GPR:ro, GPR:ro.
fdiv GPR:wo, GPR:ro, GPR:ro.
flts GPR:wo, GPR:ro.
fltu GPR:wo, GPR:ro.
fmul GPR:wo, GPR:ro, GPR:ro.
fsub GPR:wo, GPR:ro, GPR:ro.
ftrunc GPR:wo, GPR:ro.
ld GPR:wo, GPRINC:rw.
ld GPR:wo, GPROFFSET+GPRGPR+LABEL:ro.
ldb GPR:wo, GPROFFSET+GPRGPR+LABEL:ro.
@ -1511,36 +1514,32 @@ PATTERNS
nop
pat loc loc cfi $1==$2 && $1==QUAD /* Convert float -> integer */
leaving
loc 0
#if 0
cal ".cfi"
lfr QUAD
#endif
with GPR
uses reusing %1, REG
gen
ftrunc %a, %1
yields %a
pat loc loc cfu $1==$2 && $1==QUAD /* Convert float -> unsigned */
leaving
loc 0
#if 0
cal ".cfu"
lfr QUAD
#endif
with GPR
uses reusing %1, REG
gen
ftrunc %a, %1
yields %a
pat loc loc cif $1==$2 && $1==QUAD /* Convert integer -> float */
leaving
loc 0
#if 0
cal ".cif"
lfr QUAD
#endif
with GPR
uses reusing %1, REG
gen
flts %a, %1
yields %a
pat loc loc cuf $1==$2 && $1==QUAD /* Convert unsigned -> float */
leaving
loc 0
#if 0
cal ".cuf"
lfr QUAD
#endif
with GPR
uses reusing %1, REG
gen
fltu %a, %1
yields %a
pat fef /* Split float */
leaving