Added support for floating point processor
This commit is contained in:
ceriel
parent
4a03769a47
commit
e64fb88a5d
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@ -10,9 +10,12 @@
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#define low3(z) ((short)(z) & 07)
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#define low4(z) ((short)(z) & 017)
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#define low7(z) ((short)(z) & 0177)
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#define fit3(z) ((((z)-1) & ~((int)07)) == 0)
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#define fit4(z) (((z) & ~((int)017)) == 0)
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#define fit7(z) (((z) & ~((int)0177)) == 0)
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#define sfit7(z) (fit7((z)+64))
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#define fit8(z) (((z) & ~((int)0xFF)) == 0)
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#define fit16(z) (((z) & ~(0xFFFFL)) == 0)
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@ -22,6 +25,17 @@
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#define SIZE_NON 0300
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#define SIZE_DEF SIZE_W
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#define FSIZE_L 00
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#define FSIZE_S 01
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#define FSIZE_X 02
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#define FSIZE_P 03
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#define FSIZE_W 04
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#define FSIZE_D 05
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#define FSIZE_B 06
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#define DEF_FP 01000 /* default floating point processor */
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extern int co_id;
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extern int mrg_1,mrg_2;
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extern expr_t exp_1,exp_2;
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#ifndef ASLD
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@ -42,6 +42,24 @@
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%token <y_word> OP_EXT
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%token <y_word> RTD
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%token <y_word> MODEL
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%token <y_word> FPCR
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%token <y_word> FPREG
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%token <y_word> FMOVE
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%token <y_word> FMOVECR
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%token <y_word> FMOVEM
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%token <y_word> FDYADIC
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%token <y_word> FMONADIC
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%token <y_word> FSINCOS
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%token <y_word> FBCC
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%token <y_word> FDBCC
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%token <y_word> FNOP
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%token <y_word> FSCC
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%token <y_word> FTST
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%token <y_word> FSAVRES
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%token <y_word> FTRAPCC
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%token <y_word> FSIZE
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%token <y_word> CP
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%type <y_word> bcdx op_ea regs rrange
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%type <y_word> reg sizedef sizenon creg
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%type <y_word> fsize fregs fcregs frlist frrange
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@ -176,3 +176,214 @@
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0, LEA, 0, "lea",
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0, RTD, 0, "rtd",
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/* floating point coprocessor ... */
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0, FSIZE, FSIZE_S, ".s",
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0, FSIZE, FSIZE_X, ".x",
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0, FSIZE, FSIZE_P, ".p",
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0, FSIZE, FSIZE_D, ".d",
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0, FPREG, 0, "fp0",
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0, FPREG, 1, "fp1",
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0, FPREG, 2, "fp2",
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0, FPREG, 3, "fp3",
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0, FPREG, 4, "fp4",
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0, FPREG, 5, "fp5",
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0, FPREG, 6, "fp6",
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0, FPREG, 7, "fp7",
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0, FPCR, 1, "fpiar",
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0, FPCR, 2, "fpsr",
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0, FPCR, 4, "fpcr",
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0, FMOVE, 0, "fmove",
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0, FMOVECR, 0, "fmovecr",
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0, FMOVEM, 0, "fmovem",
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0, FDYADIC, 042, "fadd",
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0, FDYADIC, 070, "fcmp",
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0, FDYADIC, 040, "fdiv",
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0, FDYADIC, 041, "fmod",
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0, FDYADIC, 043, "fmul",
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0, FDYADIC, 045, "frem",
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0, FDYADIC, 046, "fscale",
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0, FDYADIC, 044, "fsgldiv",
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0, FDYADIC, 047, "fsglmul",
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0, FDYADIC, 050, "fsub",
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0, FMONADIC, 030, "fabs",
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0, FMONADIC, 034, "facos",
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0, FMONADIC, 014, "fasin",
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0, FMONADIC, 012, "fatan",
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0, FMONADIC, 015, "fatanh",
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0, FMONADIC, 035, "fcos",
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0, FMONADIC, 031, "fcosh",
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0, FMONADIC, 020, "fetox",
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0, FMONADIC, 010, "fetoxm1",
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0, FMONADIC, 036, "fgetexp",
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0, FMONADIC, 037, "fgetman",
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0, FMONADIC, 001, "fint",
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0, FMONADIC, 003, "fintrz",
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0, FMONADIC, 024, "flogn",
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0, FMONADIC, 006, "flognp1",
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0, FMONADIC, 025, "flog10",
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0, FMONADIC, 026, "flog2",
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0, FMONADIC, 032, "fneg",
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0, FMONADIC, 016, "fsin",
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0, FMONADIC, 002, "fsinh",
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0, FMONADIC, 004, "fsqrt",
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0, FMONADIC, 017, "ftan",
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0, FMONADIC, 011, "ftanh",
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0, FMONADIC, 022, "ftentox",
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0, FMONADIC, 021, "ftwotox",
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0, FSINCOS, 060, "fsincos",
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0, FBCC, 001, "fbeq",
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0, FBCC, 016, "fbne",
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0, FBCC, 022, "fbgt",
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0, FBCC, 035, "fbngt",
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0, FBCC, 023, "fbge",
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0, FBCC, 034, "fbnge",
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0, FBCC, 024, "fblt",
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0, FBCC, 033, "fbnlt",
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0, FBCC, 025, "fble",
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0, FBCC, 032, "fbnle",
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0, FBCC, 026, "fbgl",
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0, FBCC, 031, "fbngl",
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0, FBCC, 027, "fbgle",
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0, FBCC, 030, "fbngle",
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0, FBCC, 002, "fbogt",
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0, FBCC, 015, "fbule",
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0, FBCC, 003, "fboge",
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0, FBCC, 014, "fbult",
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0, FBCC, 004, "fbolt",
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0, FBCC, 013, "fbuge",
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0, FBCC, 005, "fbole",
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0, FBCC, 012, "fbugt",
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0, FBCC, 006, "fbogl",
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0, FBCC, 011, "fbueq",
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0, FBCC, 007, "fbor",
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0, FBCC, 010, "fbun",
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0, FBCC, 000, "fbf",
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0, FBCC, 017, "fbt",
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0, FBCC, 020, "fbsf",
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0, FBCC, 037, "fbst",
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0, FBCC, 021, "fbseq",
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0, FBCC, 036, "fbsne",
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0, FDBCC, 001, "fdbeq",
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0, FDBCC, 016, "fdbne",
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0, FDBCC, 022, "fdbgt",
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0, FDBCC, 035, "fdbngt",
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0, FDBCC, 023, "fdbge",
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0, FDBCC, 034, "fdbnge",
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0, FDBCC, 024, "fdblt",
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0, FDBCC, 033, "fdbnlt",
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0, FDBCC, 025, "fdble",
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0, FDBCC, 032, "fdbnle",
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0, FDBCC, 026, "fdbgl",
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0, FDBCC, 031, "fdbngl",
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0, FDBCC, 027, "fdbgle",
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0, FDBCC, 030, "fdbngle",
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0, FDBCC, 002, "fdbogt",
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0, FDBCC, 015, "fdbule",
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0, FDBCC, 003, "fdboge",
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0, FDBCC, 014, "fdbult",
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0, FDBCC, 004, "fdbolt",
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0, FDBCC, 013, "fdbuge",
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0, FDBCC, 005, "fdbole",
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0, FDBCC, 012, "fdbugt",
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0, FDBCC, 006, "fdbogl",
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0, FDBCC, 011, "fdbueq",
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0, FDBCC, 007, "fdbor",
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0, FDBCC, 010, "fdbun",
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0, FDBCC, 000, "fdbf",
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0, FDBCC, 017, "fdbt",
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0, FDBCC, 020, "fdbsf",
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0, FDBCC, 037, "fdbst",
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0, FDBCC, 021, "fdbseq",
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0, FDBCC, 036, "fdbsne",
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0, FNOP, 0, "fnop",
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0, FSCC, 001, "fseq",
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0, FSCC, 016, "fsne",
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0, FSCC, 022, "fsgt",
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0, FSCC, 035, "fsngt",
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0, FSCC, 023, "fsge",
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0, FSCC, 034, "fsnge",
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0, FSCC, 024, "fslt",
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0, FSCC, 033, "fsnlt",
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0, FSCC, 025, "fsle",
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0, FSCC, 032, "fsnle",
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0, FSCC, 026, "fsgl",
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0, FSCC, 031, "fsngl",
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0, FSCC, 027, "fsgle",
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0, FSCC, 030, "fsngle",
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0, FSCC, 002, "fsogt",
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0, FSCC, 015, "fsule",
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0, FSCC, 003, "fsoge",
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0, FSCC, 014, "fsult",
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0, FSCC, 004, "fsolt",
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0, FSCC, 013, "fsuge",
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0, FSCC, 005, "fsole",
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0, FSCC, 012, "fsugt",
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0, FSCC, 006, "fsogl",
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0, FSCC, 011, "fsueq",
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0, FSCC, 007, "fsor",
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0, FSCC, 010, "fsun",
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0, FSCC, 000, "fsf",
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0, FSCC, 017, "fst",
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0, FSCC, 020, "fssf",
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0, FSCC, 037, "fsst",
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0, FSCC, 021, "fsseq",
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0, FSCC, 036, "fssne",
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0, FTST, 0, "ftst",
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0, FSAVRES, MEM|ALT|0430, "fsave",
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0, FSAVRES, MEM|0540, "frestore",
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0, FTRAPCC, 001, "ftrapeq",
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0, FTRAPCC, 016, "ftrapne",
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0, FTRAPCC, 022, "ftrapgt",
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0, FTRAPCC, 035, "ftrapngt",
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0, FTRAPCC, 023, "ftrapge",
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0, FTRAPCC, 034, "ftrapnge",
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0, FTRAPCC, 024, "ftraplt",
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0, FTRAPCC, 033, "ftrapnlt",
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0, FTRAPCC, 025, "ftraple",
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0, FTRAPCC, 032, "ftrapnle",
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0, FTRAPCC, 026, "ftrapgl",
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0, FTRAPCC, 031, "ftrapngl",
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0, FTRAPCC, 027, "ftrapgle",
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0, FTRAPCC, 030, "ftrapngle",
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0, FTRAPCC, 002, "ftrapogt",
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0, FTRAPCC, 015, "ftrapule",
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0, FTRAPCC, 003, "ftrapoge",
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0, FTRAPCC, 014, "ftrapult",
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0, FTRAPCC, 004, "ftrapolt",
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0, FTRAPCC, 013, "ftrapuge",
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0, FTRAPCC, 005, "ftrapole",
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0, FTRAPCC, 012, "ftrapugt",
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0, FTRAPCC, 006, "ftrapogl",
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0, FTRAPCC, 011, "ftrapueq",
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0, FTRAPCC, 007, "ftrapor",
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0, FTRAPCC, 010, "ftrapun",
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0, FTRAPCC, 000, "ftrapf",
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0, FTRAPCC, 017, "ftrapt",
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0, FTRAPCC, 020, "ftrapsf",
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0, FTRAPCC, 037, "ftrapst",
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0, FTRAPCC, 021, "ftrapseq",
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0, FTRAPCC, 036, "ftrapsne",
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0, CP, 00000, "c0",
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0, CP, 01000, "c1",
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0, CP, 02000, "c2",
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0, CP, 03000, "c3",
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0, CP, 04000, "c4",
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0, CP, 05000, "c5",
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0, CP, 06000, "c6",
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0, CP, 07000, "c7",
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@ -113,6 +113,7 @@ operation
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}
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| MODEL
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{ model = $1;}
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| fp_op
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;
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bcdx : ABCD
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| ADDX sizedef
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@ -198,3 +199,222 @@ ea_ea : ea ','
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}
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ea
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;
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fp_op : CP
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{ co_id = $1; }
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fp_op1
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| { co_id = DEF_FP; }
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fp_op1
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;
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fp_op1 : FMOVE fsize ea ',' FPCR
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{ check_fsize($2, FSIZE_L);
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if ((mrg_2&070) == 010 && $5 != 001)
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badoperand();
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emit2((0170000|co_id|mrg_2));
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emit2((0100000|($5<<10)));
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ea_2(SIZE_L, 0);
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}
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| FMOVE fsize FPCR ',' ea
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{ check_fsize($2, FSIZE_L);
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if ((mrg_2&070) == 010 && $3 == 001)
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badoperand();
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emit2((0170000|co_id|mrg_2));
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emit2((0120000|($3<<10)));
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ea_2(SIZE_L, ALT);
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}
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| FMOVE fsize FPREG ',' FPREG
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{ emit2(0170000|co_id);
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emit2(($3<<10)|($5<<7));
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}
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| FMOVE fsize ea ',' FPREG
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{ ch_sz_dreg($2, mrg_2&070);
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emit2((0170000|co_id|mrg_2));
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emit2((0040000|($2<<10)|($5<<7)));
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ea_2(SIZE_L, DTA);
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}
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| FMOVE fsize FPREG ',' ea
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{ ch_sz_dreg($2, mrg_2&070);
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if ($2 == FSIZE_P)
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serror("packed decimal needs k-factor");
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emit2((0170000|co_id|mrg_2));
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emit2((0060000|($2<<10)|($3<<7)));
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ea_2(SIZE_L, DTA|ALT);
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}
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| FMOVE fsize FPREG ',' ea '{' '#' absexp '}'
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{ check_fsize($2, FSIZE_P);
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fit(sfit7($8));
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emit2((0170000|co_id|mrg_2));
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emit2((0066000|($3<<7)|low7($8)));
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ea_2(SIZE_L, MEM|DTA|ALT);
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}
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| FMOVE fsize FPREG ',' ea '{' DREG '}'
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{ check_fsize($2, FSIZE_P);
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emit2((0170000|co_id|mrg_2));
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emit2((0076000|($3<<7)|($7<<4)));
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ea_2(SIZE_L, MEM|DTA|ALT);
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}
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| FMOVECR fsize '#' absexp ',' FPREG
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{ fit(fit7($4));
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check_fsize($2, FSIZE_X);
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emit2(0170000|co_id);
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emit2(056000|($6<<7)|low7($4));
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}
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| FMOVEM FSIZE fregs ',' notimmreg
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{ check_fsize($2, FSIZE_X);
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if ((mrg_2&070) == 030)
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serror("bad addressing category");
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emit2((0170000|co_id|mrg_2));
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emit2(0160000 |
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(((mrg_2&070)==040 || ($3&04000)) ?
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$3 :
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(010000|reverse($3,8))));
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ea_2(SIZE_L, MEM|ALT);
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}
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| FMOVEM FSIZE notimmreg ',' fregs
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{ check_fsize($2, FSIZE_X);
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if ((mrg_2&070) == 040)
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serror("bad addressing category");
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emit2((0170000|co_id|mrg_2));
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emit2((0150000|(($5&04000)?$5:reverse($5,8))));
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ea_2(SIZE_L, MEM);
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}
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| FMOVEM SIZE fcregs ',' ea
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{ checksize($2, 4);
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if ((mrg_2&070) == 1 && $3!= 02000)
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serror("bad addressing category");
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if ((mrg_2 & 070) == 0 &&
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$3 != 02000 && $3 != 04000 && $3 != 010000)
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serror("bad addressing category");
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emit2((0170000|co_id|mrg_2));
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emit2((0120000|$3));
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ea_2(SIZE_L, ALT);
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}
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| FMOVEM SIZE ea ',' fcregs
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{ checksize($2, 4);
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if ((mrg_2&070) == 1 && $5!= 02000)
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serror("bad addressing category");
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if ((mrg_2 & 070) == 0 &&
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$5 != 02000 && $5 != 04000 && $5 != 010000)
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serror("bad addressing category");
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emit2((0170000|co_id|mrg_2));
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emit2((0100000|$5));
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ea_2(SIZE_L, 0);
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}
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| FDYADIC fsize ea ',' FPREG
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{ emit2((0170000|co_id|mrg_2));
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emit2((0040000|($2<<10)|($5<<7)|$1));
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ch_sz_dreg($2, mrg_2&070);
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ea_2(SIZE_L, DTA);
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}
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| FDYADIC fsize FPREG ',' FPREG
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{ check_fsize($2, FSIZE_X);
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emit2(0170000|co_id);
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emit2(($3<<10)|($5<<7)|$1);
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}
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| FMONADIC fsize ea ',' FPREG
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{ emit2((0170000|co_id|mrg_2));
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emit2((0040000|($2<<10)|($5<<7)|$1));
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ch_sz_dreg($2, mrg_2&070);
|
||||
ea_2(SIZE_L, DTA);
|
||||
}
|
||||
| FMONADIC fsize FPREG ',' FPREG
|
||||
{ check_fsize($2, FSIZE_X);
|
||||
emit2(0170000|co_id);
|
||||
emit2(($3<<10)|($5<<7)|$1);
|
||||
}
|
||||
| FMONADIC fsize FPREG
|
||||
{ check_fsize($2, FSIZE_X);
|
||||
emit2(0170000|co_id);
|
||||
emit2(($3<<10)|($3<<7)|$1);
|
||||
}
|
||||
| FSINCOS fsize ea ',' FPREG ':' FPREG
|
||||
{ emit2(0170000|co_id|mrg_2);
|
||||
emit2(0040000|($2<<10)|($7<<7)|$1|$5);
|
||||
ea_2(SIZE_L, DTA);
|
||||
}
|
||||
| FSINCOS fsize FPREG ',' FPREG ':' FPREG
|
||||
{ check_fsize($2, FSIZE_X);
|
||||
emit2(0170000|co_id);
|
||||
emit2(($3<<10)|($7<<7)|$1|$5);
|
||||
}
|
||||
| FBCC expr
|
||||
{ fbranch($1, $2);}
|
||||
| FDBCC DREG ',' expr
|
||||
{ emit2(0170110|co_id|$2);
|
||||
emit2($1);
|
||||
$4.val -= DOTVAL;
|
||||
fit(fitw($4.val));
|
||||
#ifdef RELOCATION
|
||||
newrelo($4.typ, RELPC|RELO2|RELBR|RELWR);
|
||||
#endif
|
||||
emit2(loww($4.val));
|
||||
}
|
||||
| FNOP
|
||||
{ emit2(0170200|co_id);
|
||||
emit2(0);
|
||||
}
|
||||
| FSCC ea
|
||||
{ emit2(0170100|co_id|mrg_2);
|
||||
emit2($1);
|
||||
ea_2(SIZE_B, DTA|ALT);
|
||||
}
|
||||
| FTST fsize ea
|
||||
{ emit2((0170000|co_id|mrg_2));
|
||||
emit2((0040072|($2<<10)));
|
||||
ch_sz_dreg($2, mrg_2&070);
|
||||
ea_2(SIZE_L, DTA);
|
||||
}
|
||||
| FTST fsize FPREG
|
||||
{ check_fsize($2, FSIZE_X);
|
||||
emit2(0170000|co_id);
|
||||
emit2(($3<<10)|072);
|
||||
}
|
||||
| FSAVRES ea
|
||||
{ if ((mrg_2&070) == ($1&070))
|
||||
badoperand();
|
||||
emit2((0170000|co_id|($1&0700)|mrg_2));
|
||||
ea_2(0, $1&07);
|
||||
}
|
||||
| FTRAPCC
|
||||
{ emit2(0170174|co_id);
|
||||
emit2($1);
|
||||
}
|
||||
| FTRAPCC SIZE imm
|
||||
{ checksize($2, 2|4);
|
||||
emit2((0170170|co_id|($2==SIZE_L?03:02)));
|
||||
emit2($1);
|
||||
ea_2($2,0);
|
||||
}
|
||||
;
|
||||
fregs : DREG
|
||||
{ $$ = 04000 | $1 << 4; }
|
||||
| frlist
|
||||
;
|
||||
frlist : frrange
|
||||
| frlist '/' frrange
|
||||
{ $$ = $1 | $3;}
|
||||
;
|
||||
frrange : FPREG
|
||||
{ $$ = 1 << $1; }
|
||||
| FPREG '-' FPREG
|
||||
{ if ($1 > $3)
|
||||
badoperand();
|
||||
for ($$ = 0; $1 <= $3; $1++)
|
||||
$$ |= (1 << $1);
|
||||
}
|
||||
;
|
||||
fcregs : FPCR
|
||||
{ $$ = $1 << 10; }
|
||||
| fcregs '/' FPCR
|
||||
{ $$ = $1 | ($3 << 10); }
|
||||
;
|
||||
fsize : /* empty */
|
||||
{ $$ = FSIZE_X; }
|
||||
| SIZE
|
||||
{ if ($1 == SIZE_L)
|
||||
$$ = FSIZE_L;
|
||||
else if ($1 == SIZE_W)
|
||||
$$ = FSIZE_W;
|
||||
else $$ = FSIZE_B;
|
||||
}
|
||||
| FSIZE
|
||||
;
|
||||
|
|
|
|||
|
|
@ -286,19 +286,27 @@ move_special(sz)
|
|||
badoperand();
|
||||
}
|
||||
|
||||
int
|
||||
reverse(regs, max)
|
||||
register int regs;
|
||||
{
|
||||
register int r, i;
|
||||
|
||||
r = regs; regs = 0;
|
||||
for (i = max; i > 0; i--) {
|
||||
regs <<= 1;
|
||||
if (r & 1) regs++;
|
||||
r >>= 1;
|
||||
}
|
||||
return regs;
|
||||
}
|
||||
|
||||
movem(dr, sz, regs)
|
||||
{
|
||||
register i;
|
||||
register r;
|
||||
|
||||
if ((mrg_2>>3) == 04) {
|
||||
r = regs; regs = 0;
|
||||
for (i = 0; i < 16; i++) {
|
||||
regs <<= 1;
|
||||
if (r & 1)
|
||||
regs++;
|
||||
r >>= 1;
|
||||
}
|
||||
regs = reverse(regs, 16);
|
||||
}
|
||||
checksize(sz, 2|4);
|
||||
if ((mrg_2>>3)-3 == dr)
|
||||
|
|
@ -454,3 +462,43 @@ Xnofit()
|
|||
{
|
||||
if (pass == PASS_3) serror("too big");
|
||||
}
|
||||
|
||||
fbranch(opc, exp)
|
||||
expr_t exp;
|
||||
{
|
||||
register sm;
|
||||
|
||||
exp.val -= (DOTVAL + 2);
|
||||
if ((pass == PASS_2)
|
||||
&&
|
||||
(exp.val > 0)
|
||||
&&
|
||||
((exp.typ & S_DOT) == 0)
|
||||
)
|
||||
exp.val -= DOTGAIN;
|
||||
sm = fitw(exp.val);
|
||||
if ((exp.typ & ~S_DOT) != DOTTYP)
|
||||
sm = 0;
|
||||
if (small(sm,2)) {
|
||||
emit2(0170200|co_id|opc);
|
||||
emit2(loww(exp.val));
|
||||
return;
|
||||
}
|
||||
emit2(0170300|co_id|opc); /* 4 byte offset */
|
||||
#ifdef RELOCATION
|
||||
newrelo(exp.typ, RELPC|RELO4|RELBR|RELWR);
|
||||
#endif
|
||||
emit4(exp.val);
|
||||
}
|
||||
|
||||
ch_sz_dreg(size, mode)
|
||||
{
|
||||
if (mode == 0 &&
|
||||
(size == FSIZE_X || size == FSIZE_P || size == FSIZE_D))
|
||||
serror("illegal size for data register");
|
||||
}
|
||||
|
||||
check_fsize(sz, size)
|
||||
{
|
||||
if (sz != size) serror("bad size");
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue