Yikes! Turns out that FPU registers are only 32 bits wide, and doubles are
stored in pairs, just like on the PowerPC!
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ec46643124
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e88670dad4
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@ -9,12 +9,12 @@
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.c_ud_i:
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/* Input: f0
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* Output: r2
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* Only at and f31 may be used.
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* Only at and f30/f31 may be used.
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*/
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ori at, zero, hi16[.fd_80000000]
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ldc1 f31, lo16[.fd_80000000] (at)
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c.le.d 0, f31, f0
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ldc1 f30, lo16[.fd_80000000] (at)
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c.le.d 0, f30, f0
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bc1t toobig
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nop
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@ -24,7 +24,7 @@
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nop
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toobig:
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sub.d f0, f0, f31
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sub.d f0, f0, f30
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trunc.w.d f0, f0
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mfc1 r2, f0
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addiu r2, r2, 0x8000
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@ -9,12 +9,12 @@
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.c_uf_i:
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/* Input: f0
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* Output: r2
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* Only at and f31 may be used.
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* Only at and f30/f31 may be used.
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*/
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ori at, zero, hi16[.ff_80000000]
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lwc1 f31, lo16[.ff_80000000] (at)
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c.le.s 0, f31, f0
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lwc1 f30, lo16[.ff_80000000] (at)
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c.le.s 0, f30, f0
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bc1t toobig
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nop
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@ -24,7 +24,7 @@
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nop
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toobig:
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sub.s f0, f0, f31
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sub.s f0, f0, f30
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trunc.w.s f0, f0
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mfc1 r2, f0
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addiu r2, r2, 0x8000
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@ -320,15 +320,15 @@ struct hop* platform_swap(struct basicblock* bb, struct hreg* src, struct hreg*
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break;
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case burm_float_ATTR:
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hop_add_insel(hop, "mov.s f31, %H", src);
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hop_add_insel(hop, "mov.s f30, %H", src);
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hop_add_insel(hop, "mov.s %H, %H", src, dest);
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hop_add_insel(hop, "mov.s %H, f31", dest);
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hop_add_insel(hop, "mov.s %H, f30", dest);
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break;
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case burm_double_ATTR:
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hop_add_insel(hop, "mov.d f31, %H", src);
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hop_add_insel(hop, "mov.d f30, %H", src);
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hop_add_insel(hop, "mov.d %H, %H", src, dest);
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hop_add_insel(hop, "mov.d %H, f31", dest);
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hop_add_insel(hop, "mov.d %H, f30", dest);
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break;
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}
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@ -75,41 +75,24 @@ REGISTERS
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f27 float;
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f28 float;
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f29 float;
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f30 float;
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/* f31 is used by the compiler as a temporary. */
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/* f30 and f31 is used by the compiler as a temporary. */
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d0 named("f0") aliases(f0) double volatile dret;
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d1 named("f1") aliases(f1) double volatile;
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d2 named("f2") aliases(f2) double volatile;
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d3 named("f3") aliases(f3) double volatile;
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d4 named("f4") aliases(f4) double volatile;
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d5 named("f5") aliases(f5) double volatile;
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d6 named("f6") aliases(f6) double volatile;
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d7 named("f7") aliases(f7) double volatile;
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d8 named("f8") aliases(f8) double volatile;
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d9 named("f9") aliases(f9) double volatile;
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d10 named("f10") aliases(f10) double volatile;
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d11 named("f11") aliases(f11) double volatile;
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d12 named("f12") aliases(f12) double volatile;
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d13 named("f13") aliases(f13) double volatile;
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d14 named("f14") aliases(f14) double volatile;
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d15 named("f15") aliases(f15) double volatile;
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d16 named("f16") aliases(f16) double volatile;
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d17 named("f17") aliases(f17) double volatile;
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d18 named("f18") aliases(f18) double volatile;
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d19 named("f19") aliases(f19) double volatile;
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d0 named("f0") aliases(f0, f1) double volatile dret;
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d2 named("f2") aliases(f2, f3) double volatile;
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d4 named("f4") aliases(f4, f5) double volatile;
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d6 named("f6") aliases(f6, f7) double volatile;
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d8 named("f8") aliases(f8, f9) double volatile;
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d10 named("f10") aliases(f10, f11) double volatile;
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d12 named("f12") aliases(f12, f13) double volatile;
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d14 named("f14") aliases(f14, f15) double volatile;
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d16 named("f16") aliases(f16, f17) double volatile;
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d18 named("f18") aliases(f18, f19) double volatile;
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d20 named("f20") aliases(f20) double;
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d21 named("f21") aliases(f21) double;
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d22 named("f22") aliases(f22) double;
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d23 named("f23") aliases(f23) double;
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d24 named("f24") aliases(f24) double;
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d25 named("f25") aliases(f25) double;
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d26 named("f26") aliases(f26) double;
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d27 named("f27") aliases(f27) double;
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d28 named("f28") aliases(f28) double;
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d29 named("f29") aliases(f29) double;
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d30 named("f30") aliases(f30) double;
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d20 named("f20") aliases(f20, f21) double;
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d22 named("f22") aliases(f22, f23) double;
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d24 named("f24") aliases(f24, f25) double;
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d26 named("f26") aliases(f26, f27) double;
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d28 named("f28") aliases(f28, f29) double;
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@ -425,7 +408,7 @@ PATTERNS
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FARJUMP(addr:LABEL.I)
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with corrupted(volatile)
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emit "b $addr"
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emit "j $addr"
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emit "nop"
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cost 8;
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@ -458,7 +441,7 @@ PATTERNS
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#define CALLLABEL(insn) \
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insn (dest:LABEL.I) \
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with corrupted(volatile) \
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emit "bal $dest" \
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emit "jal $dest" \
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emit "nop" \
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cost 8;
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@ -695,8 +678,8 @@ PATTERNS
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cost 30;
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out:(int)reg = FROMSD.I(in:(double)reg)
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emit "trunc.w.d f31, %in"
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emit "mfc1 %out, f31"
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emit "trunc.w.d f30, %in"
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emit "mfc1 %out, f30"
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cost 8;
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out:(lret)reg = FROMSD.L(in:(dret)reg)
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@ -748,8 +731,8 @@ PATTERNS
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cost 4;
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out:(int)reg = FROMSF.I(in:(float)reg)
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emit "trunc.w.s f31, %in"
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emit "mfc1 %out, f31"
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emit "trunc.w.s f30, %in"
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emit "mfc1 %out, f30"
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cost 8;
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out:(lret)reg = FROMSF.L(in:(fret)reg)
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