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Yikes! Turns out that FPU registers are only 32 bits wide, and doubles are

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stored in pairs, just like on the PowerPC!
This commit is contained in:
David Given 2018-09-09 18:25:00 +02:00
parent ec46643124
commit e88670dad4
4 changed files with 34 additions and 51 deletions
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8
mach/mips/libem/c_ud_i.s
View file

@ -9,12 +9,12 @@
.c_ud_i: .c_ud_i:
/* Input: f0 /* Input: f0
* Output: r2 * Output: r2
* Only at and f31 may be used. * Only at and f30/f31 may be used.
*/ */
ori at, zero, hi16[.fd_80000000] ori at, zero, hi16[.fd_80000000]
ldc1 f31, lo16[.fd_80000000] (at) ldc1 f30, lo16[.fd_80000000] (at)
c.le.d 0, f31, f0 c.le.d 0, f30, f0
bc1t toobig bc1t toobig
nop nop
@ -24,7 +24,7 @@
nop nop
toobig: toobig:
sub.d f0, f0, f31 sub.d f0, f0, f30
trunc.w.d f0, f0 trunc.w.d f0, f0
mfc1 r2, f0 mfc1 r2, f0
addiu r2, r2, 0x8000 addiu r2, r2, 0x8000

8
mach/mips/libem/c_uf_i.s
View file

@ -9,12 +9,12 @@
.c_uf_i: .c_uf_i:
/* Input: f0 /* Input: f0
* Output: r2 * Output: r2
* Only at and f31 may be used. * Only at and f30/f31 may be used.
*/ */
ori at, zero, hi16[.ff_80000000] ori at, zero, hi16[.ff_80000000]
lwc1 f31, lo16[.ff_80000000] (at) lwc1 f30, lo16[.ff_80000000] (at)
c.le.s 0, f31, f0 c.le.s 0, f30, f0
bc1t toobig bc1t toobig
nop nop
@ -24,7 +24,7 @@
nop nop
toobig: toobig:
sub.s f0, f0, f31 sub.s f0, f0, f30
trunc.w.s f0, f0 trunc.w.s f0, f0
mfc1 r2, f0 mfc1 r2, f0
addiu r2, r2, 0x8000 addiu r2, r2, 0x8000

8
mach/mips/mcg/platform.c
View file

@ -320,15 +320,15 @@ struct hop* platform_swap(struct basicblock* bb, struct hreg* src, struct hreg*
break; break;
case burm_float_ATTR: case burm_float_ATTR:
hop_add_insel(hop, "mov.s f31, %H", src); hop_add_insel(hop, "mov.s f30, %H", src);
hop_add_insel(hop, "mov.s %H, %H", src, dest); hop_add_insel(hop, "mov.s %H, %H", src, dest);
hop_add_insel(hop, "mov.s %H, f31", dest); hop_add_insel(hop, "mov.s %H, f30", dest);
break; break;
case burm_double_ATTR: case burm_double_ATTR:
hop_add_insel(hop, "mov.d f31, %H", src); hop_add_insel(hop, "mov.d f30, %H", src);
hop_add_insel(hop, "mov.d %H, %H", src, dest); hop_add_insel(hop, "mov.d %H, %H", src, dest);
hop_add_insel(hop, "mov.d %H, f31", dest); hop_add_insel(hop, "mov.d %H, f30", dest);
break; break;
} }

61
mach/mips/mcg/table
View file

@ -75,41 +75,24 @@ REGISTERS
f27 float; f27 float;
f28 float; f28 float;
f29 float; f29 float;
f30 float; /* f30 and f31 is used by the compiler as a temporary. */
/* f31 is used by the compiler as a temporary. */
d0 named("f0") aliases(f0) double volatile dret; d0 named("f0") aliases(f0, f1) double volatile dret;
d1 named("f1") aliases(f1) double volatile; d2 named("f2") aliases(f2, f3) double volatile;
d2 named("f2") aliases(f2) double volatile; d4 named("f4") aliases(f4, f5) double volatile;
d3 named("f3") aliases(f3) double volatile; d6 named("f6") aliases(f6, f7) double volatile;
d4 named("f4") aliases(f4) double volatile; d8 named("f8") aliases(f8, f9) double volatile;
d5 named("f5") aliases(f5) double volatile; d10 named("f10") aliases(f10, f11) double volatile;
d6 named("f6") aliases(f6) double volatile; d12 named("f12") aliases(f12, f13) double volatile;
d7 named("f7") aliases(f7) double volatile; d14 named("f14") aliases(f14, f15) double volatile;
d8 named("f8") aliases(f8) double volatile; d16 named("f16") aliases(f16, f17) double volatile;
d9 named("f9") aliases(f9) double volatile; d18 named("f18") aliases(f18, f19) double volatile;
d10 named("f10") aliases(f10) double volatile;
d11 named("f11") aliases(f11) double volatile;
d12 named("f12") aliases(f12) double volatile;
d13 named("f13") aliases(f13) double volatile;
d14 named("f14") aliases(f14) double volatile;
d15 named("f15") aliases(f15) double volatile;
d16 named("f16") aliases(f16) double volatile;
d17 named("f17") aliases(f17) double volatile;
d18 named("f18") aliases(f18) double volatile;
d19 named("f19") aliases(f19) double volatile;
d20 named("f20") aliases(f20) double; d20 named("f20") aliases(f20, f21) double;
d21 named("f21") aliases(f21) double; d22 named("f22") aliases(f22, f23) double;
d22 named("f22") aliases(f22) double; d24 named("f24") aliases(f24, f25) double;
d23 named("f23") aliases(f23) double; d26 named("f26") aliases(f26, f27) double;
d24 named("f24") aliases(f24) double; d28 named("f28") aliases(f28, f29) double;
d25 named("f25") aliases(f25) double;
d26 named("f26") aliases(f26) double;
d27 named("f27") aliases(f27) double;
d28 named("f28") aliases(f28) double;
d29 named("f29") aliases(f29) double;
d30 named("f30") aliases(f30) double;
@ -425,7 +408,7 @@ PATTERNS
FARJUMP(addr:LABEL.I) FARJUMP(addr:LABEL.I)
with corrupted(volatile) with corrupted(volatile)
emit "b $addr" emit "j $addr"
emit "nop" emit "nop"
cost 8; cost 8;
@ -458,7 +441,7 @@ PATTERNS
#define CALLLABEL(insn) \ #define CALLLABEL(insn) \
insn (dest:LABEL.I) \ insn (dest:LABEL.I) \
with corrupted(volatile) \ with corrupted(volatile) \
emit "bal $dest" \ emit "jal $dest" \
emit "nop" \ emit "nop" \
cost 8; cost 8;
@ -695,8 +678,8 @@ PATTERNS
cost 30; cost 30;
out:(int)reg = FROMSD.I(in:(double)reg) out:(int)reg = FROMSD.I(in:(double)reg)
emit "trunc.w.d f31, %in" emit "trunc.w.d f30, %in"
emit "mfc1 %out, f31" emit "mfc1 %out, f30"
cost 8; cost 8;
out:(lret)reg = FROMSD.L(in:(dret)reg) out:(lret)reg = FROMSD.L(in:(dret)reg)
@ -748,8 +731,8 @@ PATTERNS
cost 4; cost 4;
out:(int)reg = FROMSF.I(in:(float)reg) out:(int)reg = FROMSF.I(in:(float)reg)
emit "trunc.w.s f31, %in" emit "trunc.w.s f30, %in"
emit "mfc1 %out, f31" emit "mfc1 %out, f30"
cost 8; cost 8;
out:(lret)reg = FROMSF.L(in:(fret)reg) out:(lret)reg = FROMSF.L(in:(fret)reg)