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changed order of registers, so that d0 is allocated first

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ceriel 1989-02-06 14:35:10 +00:00
parent 76684055eb
commit eca0cde913
4 changed files with 4 additions and 4 deletions
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2
mach/m68020/ncg/table
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@ -42,7 +42,7 @@ AA_REG /* allocatable A_REG, may not be a register variable */
REGISTERS
d0, d1, d2 :D_REG, DD_REG.
d2, d1, d0 :D_REG, DD_REG.
d3, d4, d5, d6, d7 :D_REG regvar.
a0, a1 :A_REG, AA_REG.
a2, a3, a4, a5 :A_REG regvar(reg_pointer).

2
mach/m68k2/ncg/table
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@ -42,7 +42,7 @@ AA_REG /* allocatable A_REG, may not be a register variable */
REGISTERS
d0, d1, d2 :D_REG, DD_REG.
d2, d1, d0 :D_REG, DD_REG.
d3, d4, d5, d6, d7 :D_REG regvar.
a0, a1 :A_REG, AA_REG.
a2, a3, a4, a5 :A_REG regvar(reg_pointer).

2
mach/m68k4/ncg/table
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@ -42,7 +42,7 @@ AA_REG /* allocatable A_REG, may not be a register variable */
REGISTERS
d0, d1, d2 :D_REG, DD_REG.
d2, d1, d0 :D_REG, DD_REG.
d3, d4, d5, d6, d7 :D_REG regvar.
a0, a1 :A_REG, AA_REG.
a2, a3, a4, a5 :A_REG regvar(reg_pointer).

2
mach/moon3/ncg/table
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@ -42,7 +42,7 @@ AA_REG /* allocatable A_REG, may not be a register variable */
REGISTERS
d0, d1, d2 :D_REG, DD_REG.
d2, d1, d0 :D_REG, DD_REG.
d3, d4, d5, d6, d7 :D_REG regvar.
a0, a1 :A_REG, AA_REG.
a2, a3, a4, a5 :A_REG regvar(reg_pointer).