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Tweak i386 rules for adi 8, sli 8, sru 8.

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Add EXACT to the rule for adi 8, in the same way that the old rules
for and 8, ior 8, xor 8 have EXACT.

Add rules for sli 8 and sru 8 when shifting 32 bits, and add
assertions in llshift_e.c to test these rules.
This commit is contained in:
George Koehler 2019-09-18 14:09:51 -04:00
parent 6f84bc1dcf
commit f0a2c84d93
2 changed files with 9 additions and 2 deletions
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6
mach/i386/ncg/table
View file

@ -973,7 +973,7 @@ with EXACT rmorconst const
gen add %a,%2 yields %a gen add %a,%2 yields %a
pat adi $1==8 pat adi $1==8
with REG REG rmorconst rmorconst with EXACT REG REG rmorconst rmorconst
gen add %1,%3 gen add %1,%3
adc %2,%4 yields %2 %1 adc %2,%4 yields %2 %1
with rmorconst rmorconst REG REG with rmorconst rmorconst REG REG
@ -1104,6 +1104,8 @@ pat loc sli ($1&32)==0 && $2==8
with REG REG with REG REG
gen shld %2,%1,{ANYCON,$1&31} gen shld %2,%1,{ANYCON,$1&31}
sal %1,{ANYCON,$1&31} yields %2 %1 sal %1,{ANYCON,$1&31} yields %2 %1
pat loc sli ($1&63)==32 && $2==8
with a_word a_word yields %1 {ANYCON,0}
pat loc sli ($1&32)!=0 && $2==8 pat loc sli ($1&32)!=0 && $2==8
with REG REG with REG REG
gen sal %1,{ANYCON,$1&31} yields %1 {ANYCON,0} gen sal %1,{ANYCON,$1&31} yields %1 {ANYCON,0}
@ -1253,6 +1255,8 @@ pat loc sru ($1&32)==0 && $2==8
with REG REG with REG REG
gen shrd %2,%1,{ANYCON,$1&31} gen shrd %2,%1,{ANYCON,$1&31}
shr %1,{ANYCON,$1&31} yields %2 %1 shr %1,{ANYCON,$1&31} yields %2 %1
pat loc sru ($1&63)==32 && $2==8
with a_word a_word yields {ANYCON,0} %2
pat loc sru ($1&32)!=0 && $2==8 pat loc sru ($1&32)!=0 && $2==8
with REG REG with REG REG
gen shr %2,{ANYCON,$1&31} yields {ANYCON,0} %2 gen shr %2,{ANYCON,$1&31} yields {ANYCON,0} %2

5
tests/plat/long-long/llshift_e.c
View file

@ -17,6 +17,8 @@ void _m_a_i_n(void) {
ASSERT(i << (1 + zero) == 242LL); ASSERT(i << (1 + zero) == 242LL);
ASSERT(i << 26 == 8120172544LL); ASSERT(i << 26 == 8120172544LL);
ASSERT(i << (26 + zero) == 8120172544LL); ASSERT(i << (26 + zero) == 8120172544LL);
ASSERT(i << 32 == 519691042816LL);
ASSERT(i << (32 + zero) == 519691042816LL);
ASSERT(i << 56 == 8718968878589280256LL); ASSERT(i << 56 == 8718968878589280256LL);
ASSERT(i << (56 + zero) == 8718968878589280256LL); ASSERT(i << (56 + zero) == 8718968878589280256LL);
@ -67,9 +69,10 @@ void _m_a_i_n(void) {
ASSERT(u >> (0 + zero) == 12022195707510591570ULL); ASSERT(u >> (0 + zero) == 12022195707510591570ULL);
ASSERT(u >> 1 == 6011097853755295785ULL); ASSERT(u >> 1 == 6011097853755295785ULL);
ASSERT(u >> (1 + zero) == 6011097853755295785ULL); ASSERT(u >> (1 + zero) == 6011097853755295785ULL);
ASSERT(u >> 32 == 2799135564ULL);
ASSERT(u >> (32 + zero) == 2799135564ULL);
ASSERT(u >> 41 == 5467061ULL); ASSERT(u >> 41 == 5467061ULL);
ASSERT(u >> (41 + zero) == 5467061ULL); ASSERT(u >> (41 + zero) == 5467061ULL);
finished(); finished();
} }