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bugs fixed (syntax errors, patterns moved to front,

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"ldl ldl adp sdl sti" requires DATAREG instead of ANY1 on
fakestack)
This commit is contained in:
bal 1984-07-30 11:16:41 +00:00
parent 233b4aeee4
commit f2e52892ac
1 changed files with 35 additions and 41 deletions
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76
mach/m68k2/cg/table
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@ -510,6 +510,41 @@ sdf | ADDREG ANY4 | remove(MEM_ALL)
* local variables that are not register-variables. * local variables that are not register-variables.
*/ */
ldl ldl adp sdl loi $1==$2 && $2==$4 && inreg($1)==2 && $3==1 && $5==1 | |
allocate(DATAREG={IMMEDIATE,0})
remove(regvar($1))
"move.b (%(regvar($1)%))+,%[a]" | %[a] | |
ldl ldl adp sdl loi $1==$2 && $2==$4 && inreg($1)==2 && $3==2 && $5==2 | |
allocate(DATAREG)
remove(regvar($1))
"move.w (%(regvar($1)%))+,%[a]" | %[a] | |
ldl ldl adp sdl sti $1==$2 && $2==$4 && inreg($1)==2 && $3==1 && $5==1 | DATAREG |
remove(regvar($1))
"move.b %[1],(%(regvar($1)%))+" | | |
ldl ldl adp sdl sti $1==$2 && $2==$4 && inreg($1)==2 && $3==2 && $5==2 | ANY |
remove(regvar($1))
"move.w %[1],(%(regvar($1)%))+" | | |
ldl ldl adp sdl $1==$2 && $2==$4 && inreg($1)==2 | |
allocate(ADDREG=regvar($1)) | %[a]
| ldl $2 adp $3 sdl $2 |
lol inl $1==$2 && inreg($1)==2 | |
allocate(DATAREG=regvar($1)) | %[a]
| inl $2 |
lol inl $1==$2 | |
allocate(DATAREG={DISPL,LB,$1}) | %[a]
| inl $2 |
lol del $1==$2 && inreg($1)==2 | |
allocate(DATAREG=regvar($1)) | %[a]
| del $2 |
lol del $1==$2 | |
allocate(DATAREG={DISPL,LB,$1}) | %[a]
| del $2 |
loe ine $1==$2 | |
allocate(DATAREG={ABS,$1}) | %[a]
| ine $2 |
loe dee $1==$2 | |
allocate(DATAREG={ABS,$1}) | %[a]
| dee $2 |
lol adi stl $1 == $3 && $2 == 2 && inreg($1)==2 | ANY | lol adi stl $1 == $3 && $2 == 2 && inreg($1)==2 | ANY |
remove(regvar($1)) remove(regvar($1))
@ -608,11 +643,6 @@ lol loc slu stl $1 == $4 && $2 == 1 && $3 == 2 && inreg($1)==2 | |
remove(regvar($1)) remove(regvar($1))
"asl.w #1,%(regvar($1)%)" "asl.w #1,%(regvar($1)%)"
erase(regvar($1)) | | | erase(regvar($1)) | | |
ldl ldl adp sdl $1 == $2 && $2 == $4 && inreg($1)==2 | |
remove(regvar($1))
allocate(ADDREG=regvar($1))
"add.l #$3,%(regvar($1)%)"
erase(regvar($1)) | %[a] | |
ldl adp sdl $1 == $3 && inreg($1)==2 | | remove(regvar($1)) ldl adp sdl $1 == $3 && inreg($1)==2 | | remove(regvar($1))
"add.l #$2,%(regvar($1)%)" "add.l #$2,%(regvar($1)%)"
erase(regvar($1)) | | | erase(regvar($1)) | | |
@ -1168,42 +1198,6 @@ dee | |
remove(ALL_ACCESSIBLE) remove(ALL_ACCESSIBLE)
"sub.w #1,$1" "sub.w #1,$1"
setcc({ABS,$1}) | | | setcc({ABS,$1}) | | |
#ifdef REGVARS
ldl ldl adp sdl loi $1==$2 && $2==$4 && inreg($1)==2 && $3==1 && $5==1 | |
allocate(DATAREG={IMMEDIATE,0})
remove(regvar($1))
"move.b (%regvar($1)%))+,%[a]" | %[a] | |
ldl ldl adp sdl loi $1==$2 && $2==$4 && inreg($1)==2 && $3==2 && $5==2 | |
allocate(DATAREG)
remove(regvar($1))
"move.w (%regvar($1)%))+,%[a]" | %[a] | |
ldl ldl adp sdl sti $1==$2 && $2==$4 && inreg($1)==2 && $3==1 && $5==1 | ANY1 |
remove(regvar($1))
"move.b %[1],(%(regvar($1)%))+" | | |
ldl ldl adp sdl sti $1==$2 && $2==$4 && inreg($1)==2 && $3==2 && $5==2 | ANY |
remove(regvar($1))
"move.w %[1],(%(regvar($1)%))+" | | |
ldl ldl adp sdl $1==$2 && $2==$4 && inreg($1)==2 | |
allocate(ADDREG=regvar($1)) | %[a]
| ldl $2 adp $3 sdl $2 |
lol inl $1==$2 && inreg($1)==2 | |
allocate(DATAREG=regvar($1)) | %[a]
| inl $2 |
lol inl $1==$2 | |
allocate(DATAREG={DISPL,LB,$1}) | %[a]
| inl $2 |
lol del $1==$2 && inreg($1)==2 | |
allocate(DATAREG=regvar($1)) | %[a]
| del $2 |
lol del $1==$2 | |
allocate(DATAREG={DISPL,LB,$1}) | %[a]
| del $2 |
loe ine $1==$2 | |
allocate(DATAREG={ABS,$1}) | %[a]
| ine $2 |
loe dee $1==$2 | |
allocate(DATAREG={ABS,$1}) | %[a]
| dee $2 |
zrl | | remove(DISPL,%[reg] == LB && %[dis] == $1) zrl | | remove(DISPL,%[reg] == LB && %[dis] == $1)
remove(DISPL4,%[reg] == LB && (%[dis] == $1-2 || remove(DISPL4,%[reg] == LB && (%[dis] == $1-2 ||
%[dis] == $1)) %[dis] == $1))