fixed: pattern for ADI STL and the like was wrong
This commit is contained in:
ceriel
parent
101e93205b
commit
fb0051c85a
4 changed files with 40 additions and 32 deletions
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@ -45,15 +45,17 @@ D_REG /* data registers */
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A_REG /* address registers */
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DD_REG /* allocatable D_REG, may not be a register variable */
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AA_REG /* allocatable A_REG, may not be a register variable */
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RD_REG /* data register, register var */
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RA_REG /* address register, register var */
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REGISTERS
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d0, d1, d2 :D_REG, DD_REG.
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d3, d4, d5, d6, d7 :D_REG regvar.
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d3, d4, d5, d6, d7 :D_REG, RD_REG regvar.
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a0, a1 :A_REG, AA_REG.
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a2, a3, a4, a5 :A_REG regvar(reg_pointer).
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a2, a3, a4, a5 :A_REG, RA_REG regvar(reg_pointer).
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lb ("a6"), sp :A_REG. /* localbase and stack pointer */
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@ -1558,11 +1560,11 @@ pat loe lol xor ste $1==$4 && $3==4 && inreg($2)==reg_any
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call loerxxxste("eor.l")
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proc xxxstl example adi stl
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with any4 any
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with any4-RD_REG-dreg4 any-RD_REG-dreg4
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kills regvar($2, reg_any), use_index %xreg==regvar($2, reg_any)
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gen move %2,{dreg4, regvar($2)}
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xxx* %1,{LOCAL,$2}
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with exact any4 STACK
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with exact any4-RD_REG-dreg4 STACK
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kills regvar($2, reg_any), use_index %xreg==regvar($2, reg_any)
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gen move_l {post_inc4, sp}, {dreg4, regvar($2)}
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xxx* %1,{LOCAL,$2}
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@ -1576,12 +1578,12 @@ pat ior stl $1==4 && inreg($2)==reg_any call xxxstl("or.l")
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pat xor stl $1==4 && inreg($2)==reg_any call xxxstl("eor.l")
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pat ads stl $1==4 && inreg($2)==reg_pointer
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with any4 any4+address
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with any4-areg-RA_REG any4+address-areg-RA_REG
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kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
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gen move %2,{areg,regvar($2,reg_pointer)}
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add_l %1,{areg,regvar($2,reg_pointer)}
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#ifdef TBL68020
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with regX any4+address
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with regX any4+address-areg-RA_REG
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kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
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gen move %2,{areg,regvar($2,reg_pointer)}
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move {regAregXcon, regvar($2,reg_pointer), %1.xreg, %1.sc, 0},{areg,regvar($2,reg_pointer)}
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@ -1653,11 +1655,11 @@ with exact absolute4 ext_regX
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proc xxxdupstl example adi dup stl
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with any4 any
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with any4-RD_REG-dreg4 any-RD_REG-dreg4
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kills regvar($3, reg_any), use_index %xreg==regvar($3, reg_any)
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gen move %2,{dreg4, regvar($3)}
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xxx* %1,{LOCAL,$3} yields {LOCAL, $3}
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with exact any4 STACK
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with exact any4-RD_REG-dreg4 STACK
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kills regvar($3, reg_any), use_index %xreg==regvar($3, reg_any)
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gen move_l {post_inc4, sp}, {dreg4, regvar($3)}
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xxx* %1,{LOCAL,$3} yields {LOCAL, $3}
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@ -45,15 +45,17 @@ D_REG /* data registers */
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A_REG /* address registers */
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DD_REG /* allocatable D_REG, may not be a register variable */
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AA_REG /* allocatable A_REG, may not be a register variable */
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RD_REG /* data register, register var */
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RA_REG /* address register, register var */
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REGISTERS
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d0, d1, d2 :D_REG, DD_REG.
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d3, d4, d5, d6, d7 :D_REG regvar.
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d3, d4, d5, d6, d7 :D_REG, RD_REG regvar.
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a0, a1 :A_REG, AA_REG.
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a2, a3, a4, a5 :A_REG regvar(reg_pointer).
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a2, a3, a4, a5 :A_REG, RA_REG regvar(reg_pointer).
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lb ("a6"), sp :A_REG. /* localbase and stack pointer */
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@ -1558,11 +1560,11 @@ pat loe lol xor ste $1==$4 && $3==4 && inreg($2)==reg_any
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call loerxxxste("eor.l")
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proc xxxstl example adi stl
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with any4 any
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with any4-RD_REG-dreg4 any-RD_REG-dreg4
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kills regvar($2, reg_any), use_index %xreg==regvar($2, reg_any)
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gen move %2,{dreg4, regvar($2)}
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xxx* %1,{LOCAL,$2}
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with exact any4 STACK
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with exact any4-RD_REG-dreg4 STACK
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kills regvar($2, reg_any), use_index %xreg==regvar($2, reg_any)
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gen move_l {post_inc4, sp}, {dreg4, regvar($2)}
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xxx* %1,{LOCAL,$2}
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@ -1576,12 +1578,12 @@ pat ior stl $1==4 && inreg($2)==reg_any call xxxstl("or.l")
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pat xor stl $1==4 && inreg($2)==reg_any call xxxstl("eor.l")
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pat ads stl $1==4 && inreg($2)==reg_pointer
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with any4 any4+address
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with any4-areg-RA_REG any4+address-areg-RA_REG
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kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
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gen move %2,{areg,regvar($2,reg_pointer)}
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add_l %1,{areg,regvar($2,reg_pointer)}
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#ifdef TBL68020
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with regX any4+address
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with regX any4+address-areg-RA_REG
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kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
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gen move %2,{areg,regvar($2,reg_pointer)}
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move {regAregXcon, regvar($2,reg_pointer), %1.xreg, %1.sc, 0},{areg,regvar($2,reg_pointer)}
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@ -1653,11 +1655,11 @@ with exact absolute4 ext_regX
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proc xxxdupstl example adi dup stl
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with any4 any
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with any4-RD_REG-dreg4 any-RD_REG-dreg4
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kills regvar($3, reg_any), use_index %xreg==regvar($3, reg_any)
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gen move %2,{dreg4, regvar($3)}
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xxx* %1,{LOCAL,$3} yields {LOCAL, $3}
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with exact any4 STACK
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with exact any4-RD_REG-dreg4 STACK
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kills regvar($3, reg_any), use_index %xreg==regvar($3, reg_any)
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gen move_l {post_inc4, sp}, {dreg4, regvar($3)}
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xxx* %1,{LOCAL,$3} yields {LOCAL, $3}
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@ -45,15 +45,17 @@ D_REG /* data registers */
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A_REG /* address registers */
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DD_REG /* allocatable D_REG, may not be a register variable */
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AA_REG /* allocatable A_REG, may not be a register variable */
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RD_REG /* data register, register var */
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RA_REG /* address register, register var */
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REGISTERS
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d0, d1, d2 :D_REG, DD_REG.
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d3, d4, d5, d6, d7 :D_REG regvar.
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d3, d4, d5, d6, d7 :D_REG, RD_REG regvar.
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a0, a1 :A_REG, AA_REG.
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a2, a3, a4, a5 :A_REG regvar(reg_pointer).
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a2, a3, a4, a5 :A_REG, RA_REG regvar(reg_pointer).
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lb ("a6"), sp :A_REG. /* localbase and stack pointer */
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@ -1558,11 +1560,11 @@ pat loe lol xor ste $1==$4 && $3==4 && inreg($2)==reg_any
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call loerxxxste("eor.l")
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proc xxxstl example adi stl
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with any4 any
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with any4-RD_REG-dreg4 any-RD_REG-dreg4
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kills regvar($2, reg_any), use_index %xreg==regvar($2, reg_any)
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gen move %2,{dreg4, regvar($2)}
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xxx* %1,{LOCAL,$2}
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with exact any4 STACK
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with exact any4-RD_REG-dreg4 STACK
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kills regvar($2, reg_any), use_index %xreg==regvar($2, reg_any)
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gen move_l {post_inc4, sp}, {dreg4, regvar($2)}
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xxx* %1,{LOCAL,$2}
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@ -1576,12 +1578,12 @@ pat ior stl $1==4 && inreg($2)==reg_any call xxxstl("or.l")
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pat xor stl $1==4 && inreg($2)==reg_any call xxxstl("eor.l")
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pat ads stl $1==4 && inreg($2)==reg_pointer
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with any4 any4+address
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with any4-areg-RA_REG any4+address-areg-RA_REG
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kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
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gen move %2,{areg,regvar($2,reg_pointer)}
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add_l %1,{areg,regvar($2,reg_pointer)}
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#ifdef TBL68020
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with regX any4+address
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with regX any4+address-areg-RA_REG
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kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
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gen move %2,{areg,regvar($2,reg_pointer)}
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move {regAregXcon, regvar($2,reg_pointer), %1.xreg, %1.sc, 0},{areg,regvar($2,reg_pointer)}
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@ -1653,11 +1655,11 @@ with exact absolute4 ext_regX
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proc xxxdupstl example adi dup stl
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with any4 any
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with any4-RD_REG-dreg4 any-RD_REG-dreg4
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kills regvar($3, reg_any), use_index %xreg==regvar($3, reg_any)
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gen move %2,{dreg4, regvar($3)}
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xxx* %1,{LOCAL,$3} yields {LOCAL, $3}
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with exact any4 STACK
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with exact any4-RD_REG-dreg4 STACK
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kills regvar($3, reg_any), use_index %xreg==regvar($3, reg_any)
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gen move_l {post_inc4, sp}, {dreg4, regvar($3)}
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xxx* %1,{LOCAL,$3} yields {LOCAL, $3}
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@ -45,15 +45,17 @@ D_REG /* data registers */
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A_REG /* address registers */
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DD_REG /* allocatable D_REG, may not be a register variable */
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AA_REG /* allocatable A_REG, may not be a register variable */
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RD_REG /* data register, register var */
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RA_REG /* address register, register var */
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REGISTERS
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d0, d1, d2 :D_REG, DD_REG.
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d3, d4, d5, d6, d7 :D_REG regvar.
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d3, d4, d5, d6, d7 :D_REG, RD_REG regvar.
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a0, a1 :A_REG, AA_REG.
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a2, a3, a4, a5 :A_REG regvar(reg_pointer).
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a2, a3, a4, a5 :A_REG, RA_REG regvar(reg_pointer).
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lb ("a6"), sp :A_REG. /* localbase and stack pointer */
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@ -1558,11 +1560,11 @@ pat loe lol xor ste $1==$4 && $3==4 && inreg($2)==reg_any
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call loerxxxste("eor.l")
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proc xxxstl example adi stl
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with any4 any
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with any4-RD_REG-dreg4 any-RD_REG-dreg4
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kills regvar($2, reg_any), use_index %xreg==regvar($2, reg_any)
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gen move %2,{dreg4, regvar($2)}
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xxx* %1,{LOCAL,$2}
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with exact any4 STACK
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with exact any4-RD_REG-dreg4 STACK
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kills regvar($2, reg_any), use_index %xreg==regvar($2, reg_any)
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gen move_l {post_inc4, sp}, {dreg4, regvar($2)}
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xxx* %1,{LOCAL,$2}
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@ -1576,12 +1578,12 @@ pat ior stl $1==4 && inreg($2)==reg_any call xxxstl("or.l")
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pat xor stl $1==4 && inreg($2)==reg_any call xxxstl("eor.l")
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pat ads stl $1==4 && inreg($2)==reg_pointer
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with any4 any4+address
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with any4-areg-RA_REG any4+address-areg-RA_REG
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kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
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gen move %2,{areg,regvar($2,reg_pointer)}
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add_l %1,{areg,regvar($2,reg_pointer)}
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#ifdef TBL68020
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with regX any4+address
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with regX any4+address-areg-RA_REG
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kills regvar($2, reg_pointer), all_regind %reg==regvar($2, reg_pointer)
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gen move %2,{areg,regvar($2,reg_pointer)}
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move {regAregXcon, regvar($2,reg_pointer), %1.xreg, %1.sc, 0},{areg,regvar($2,reg_pointer)}
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@ -1653,11 +1655,11 @@ with exact absolute4 ext_regX
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proc xxxdupstl example adi dup stl
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with any4 any
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with any4-RD_REG-dreg4 any-RD_REG-dreg4
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kills regvar($3, reg_any), use_index %xreg==regvar($3, reg_any)
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gen move %2,{dreg4, regvar($3)}
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xxx* %1,{LOCAL,$3} yields {LOCAL, $3}
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with exact any4 STACK
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with exact any4-RD_REG-dreg4 STACK
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kills regvar($3, reg_any), use_index %xreg==regvar($3, reg_any)
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gen move_l {post_inc4, sp}, {dreg4, regvar($3)}
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xxx* %1,{LOCAL,$3} yields {LOCAL, $3}
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