Add register offset and postincrement memory operations.
--HG-- branch : dtrg-videocore
This commit is contained in:
David Given
parent
fc2833d456
commit
febe8ca937
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@ -9,21 +9,12 @@
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#define ALWAYS 14
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extern void alu_instr_reg(quad opcode, quad cc, quad rd,
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quad ra, quad rb);
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extern void alu_instr_lit(quad opcode, quad cc, quad rd,
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quad ra, quad value);
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extern void misc_instr_reg(quad opcode, quad cc, quad rd,
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quad ra, quad rb);
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extern void misc_instr_lit(quad opcode, quad cc, quad rd,
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quad ra, quad value);
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extern void branch_instr(quad bl, quad cc, struct expr_t* expr);
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extern void stack_instr(quad opcode, quad loreg, quad hireg,
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quad extrareg);
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extern void mem_instr(quad opcode, quad cc, quad rd, long offset, quad rs);
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extern void alu_instr_reg(quad opcode, int cc, int rd, int ra, int rb);
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extern void alu_instr_lit(quad opcode, int cc, int rd, int ra, quad value);
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extern void misc_instr_reg(quad opcode, int cc, int rd, int ra, int rb);
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extern void misc_instr_lit(quad opcode, int cc, int rd, int ra, quad value);
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extern void branch_instr(int bl, int cc, struct expr_t* expr);
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extern void stack_instr(quad opcode, int loreg, int hireg, int extrareg);
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extern void mem_instr(quad opcode, int cc, int rd, long offset, int rs);
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extern void mem_offset_instr(quad opcode, int cc, int rd, int qa, int rb);
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extern void mem_postincr_instr(quad opcode, int cc, int rd, int rs);
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@ -6,7 +6,7 @@
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*/
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operation
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: OP { emit2($1); }
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: OP { emit2($1); }
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| OP_BRANCH GPR { emit2($1 | ($2<<0)); }
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| OP_BRANCH expr { branch_instr($1, ALWAYS, &$2); }
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@ -47,10 +47,10 @@ operation
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| OP_MEM GPR ',' absexp '(' GPR ')' { mem_instr($1, ALWAYS, $2, $4, $6); }
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| OP_MEM CC GPR ',' absexp '(' GPR ')' { mem_instr($1, $2, $3, $5, $7); }
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| OP_MEM GPR ',' '(' GPR ',' GPR ')'
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| OP_MEM CC GPR ',' '(' GPR ',' GPR ')'
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| OP_MEM GPR ',' '(' GPR ',' GPR ')' { mem_offset_instr($1, ALWAYS, $2, $5, $7); }
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| OP_MEM CC GPR ',' '(' GPR ',' GPR ')' { mem_offset_instr($1, $2, $3, $6, $8); }
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| OP_MEM GPR ',' '(' GPR ')' '+' '+'
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| OP_MEM CC GPR ',' '(' GPR ')' '+' '+'
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| OP_MEM GPR ',' '(' GPR ')' '+' '+' { mem_postincr_instr($1, ALWAYS, $2, $5); }
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| OP_MEM CC GPR ',' '(' GPR ')' '+' '+' { mem_postincr_instr($1, $2, $3, $6); }
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;
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@ -9,7 +9,7 @@
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/* Assemble an ALU instruction where rb is a register. */
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void alu_instr_reg(quad op, quad cc, quad rd, quad ra, quad rb)
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void alu_instr_reg(quad op, int cc, int rd, int ra, int rb)
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{
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/* Can we use short form? */
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@ -27,7 +27,7 @@ void alu_instr_reg(quad op, quad cc, quad rd, quad ra, quad rb)
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/* Assemble an ALU instruction where rb is a literal. */
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void alu_instr_lit(quad op, quad cc, quad rd, quad ra, quad value)
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void alu_instr_lit(quad op, int cc, int rd, int ra, quad value)
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{
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/* 16 bit short form? */
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@ -68,7 +68,7 @@ void alu_instr_lit(quad op, quad cc, quad rd, quad ra, quad value)
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/* Miscellaneous instructions with three registers and a cc. */
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void misc_instr_reg(quad op, quad cc, quad rd, quad ra, quad rb)
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void misc_instr_reg(quad op, int cc, int rd, int ra, int rb)
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{
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emit2(op | (rd<<0));
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emit2(B16(00000000,00000000) | (ra<<11) | (cc<<7) | (rb<<0));
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@ -76,7 +76,7 @@ void misc_instr_reg(quad op, quad cc, quad rd, quad ra, quad rb)
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/* Miscellaneous instructions with two registers, a literal, and a cc. */
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void misc_instr_lit(quad op, quad cc, quad rd, quad ra, quad value)
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void misc_instr_lit(quad op, int cc, int rd, int ra, quad value)
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{
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if (value < 0x1f)
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serror("only constants from 0..31 can be used here");
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@ -88,7 +88,7 @@ void misc_instr_lit(quad op, quad cc, quad rd, quad ra, quad value)
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/* Assemble a branch instruction. This may be a near branch into this
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* object file, or a far branch which requires a fixup. */
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void branch_instr(quad bl, quad cc, struct expr_t* expr)
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void branch_instr(int bl, int cc, struct expr_t* expr)
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{
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quad type = expr->typ & S_TYP;
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@ -159,9 +159,9 @@ void branch_instr(quad bl, quad cc, struct expr_t* expr)
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/* Push/pop. */
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void stack_instr(quad opcode, quad loreg, quad hireg, quad extrareg)
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void stack_instr(quad opcode, int loreg, int hireg, int extrareg)
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{
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quad b;
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int b;
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switch (loreg)
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{
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@ -210,7 +210,7 @@ void stack_instr(quad opcode, quad loreg, quad hireg, quad extrareg)
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/* Memory operations where the offset is a fixed value (including zero). */
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void mem_instr(quad opcode, quad cc, quad rd, long offset, quad rs)
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void mem_instr(quad opcode, int cc, int rd, long offset, int rs)
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{
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quad uoffset = (quad) offset;
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int multiple4 = !(offset & 3);
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@ -310,3 +310,19 @@ void mem_instr(quad opcode, quad cc, quad rd, long offset, quad rs)
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serror("invalid load/store instruction");
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}
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/* Memory operations where the destination address is a sum of two
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* registers. */
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void mem_offset_instr(quad opcode, int cc, int rd, int ra, int rb)
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{
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emit2(B16(10100000,00000000) | (opcode<<5) | (rd<<0));
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emit2(B16(00000000,00000000) | (ra<<11) | (cc<<7) | (rb<<0));
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}
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/* Memory operations with postincrement. */
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void mem_postincr_instr(quad opcode, int cc, int rd, int rs)
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{
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emit2(B16(10100101,00000000) | (opcode<<5) | (rd<<0));
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emit2(B16(00000000,00000000) | (rs<<11) | (cc<<7));
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}
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@ -333,3 +333,14 @@ forward:
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st.f r0, (r1)
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ld.f r0, 8 (r1)
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st.f r0, 8 (r1)
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ld r0, (r1, r2)
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st r0, (r1, r2)
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ld.f r0, (pc, pc)
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st.f r0, (pc, pc)
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ld r0, (r1)++
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st r0, (r1)++
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ld.f pc, (pc)++
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st.f pc, (pc)++
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