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Author SHA1 Message Date
David Given
216ff5cc43 Make loads and stores in the table nicer; fix a place where it looked like it 
was working but only accidentally.
 2016-10-12 23:12:53 +02:00
David Given
f06b51c981 Keep track of register types as well as attributes --- the type being how we 
find new registers when evicting values. Input constraints work (they were
being ignored before). Various bug fixing so they actually work.
 2016-10-12 22:58:46 +02:00
David Given
4723a1442f Add code to remove unused phis, converting to pruned SSA form, to avoid 
confusing the register allocator later.
 2016-10-12 21:50:12 +02:00
David Given
df239b3f90 Don't allow the same IR to be added to the sequence list more than once 
(sometimes happens because op_dup, but makes no sense).
 2016-10-12 00:45:36 +02:00
David Given
96dffd2007 Clean up the allocator a bit, in preparation for making it lots more 
complicated; no semantic changes.
 2016-10-11 23:17:30 +02:00
David Given
668cccdff1 A few more opcodes. 2016-10-11 00:29:18 +02:00
David Given
2be1c51885 A little fiddling with store instructions. The PowerPC is not friendly to 
iburg.
 2016-10-11 00:23:35 +02:00
David Given
e93c58dc8d Refactored the way hops are rendered; add support for emitting code (although 
with no prologue or epilogue yet).
 2016-10-11 00:12:11 +02:00
David Given
92bd1ac5f4 Register allocator now gets all the way through all of my test file without 
crashing (albeit with register moves and swaps stubbed out). Correct code? Who
knows.
 2016-10-10 23:19:46 +02:00
David Given
a4d06d1795 D'oh, need multiple passes over the edge splitter in order to properly find all 
cases.
 2016-10-10 23:18:37 +02:00
David Given
fac12aae32 Calculate phi congruency groups; use them to solve the 
importing-hreg-from-the-future problem (probably poorly).
 2016-10-09 22:04:20 +02:00
David Given
23c3575f0f The register allocator now makes a spirited attempt to honour register 
attributes when allocating. Unfortunately, backward edges don't work (because
the limited def-use chain stuff doesn't work across basic blocks). Needs more
thought.
 2016-10-09 15:09:34 +02:00
David Given
38de688c5a Floating point promotion was broken since the IR float change. Fix. 2016-10-09 15:08:03 +02:00
David Given
36cddd6afb Add some more opcodes; rearrange the registers to be more PowerPC-friendly. 2016-10-09 14:45:13 +02:00
David Given
cfe5312fcc Predicates can now take numeric arguments. The PowerPC predicates have been 
turned into generic ones (as they'll be useful everywhere). Node arguments for
predicates require the '%' prefix for consistency. Hex numbers are permitted.
 2016-10-09 12:32:36 +02:00
David Given
d75cc0a663 Basic register allocation works! 2016-10-08 23:32:54 +02:00
David Given
637aeed70a Only allocate an output vreg if the instruction actually wants one. 2016-10-08 12:15:21 +02:00
David Given
2198db69b1 Instruction predicates work now. 2016-10-08 11:35:33 +02:00
David Given
9ebf731335 Minor cleanup. 2016-10-08 11:07:28 +02:00
David Given
9db902314b Fix bug where pushes were being placed in the wrong blocks. 2016-10-08 10:21:24 +02:00
David Given
4e49830e09 Overhaul of everything phi related; critical edge splitting now happens before 
anything SSA happens; liveness calculations now look like they might be
working.
 2016-10-08 00:21:23 +02:00
David Given
ee93389c5f Refactor the cfg and dominance stuff to make it a lot nicer. 2016-10-06 21:34:21 +02:00
David Given
d20b63dc94 The register allocator is really a pass, so arrange the code like one. 2016-10-05 23:55:38 +02:00
David Given
87e004e4a9 Warning fix. 2016-10-05 23:55:04 +02:00
David Given
21034c0d65 No, dammit, for register allocation I need to walk the blocks in *dominance* 
order. Since the dominance tree has changed when I fiddled with the graph, I
need to recompute it, so factor it out of the SSA pass. Code is uglier than I'd
like but at least the RET statement goes last in the generated code now.
 2016-10-05 23:52:54 +02:00
David Given
d95c75dfd7 Allowing an input filename on the command line makes debuggers happy. (Then we 
don't need to redirect stdin.)
 2016-10-05 23:24:29 +02:00
David Given
88fb231d6e Better constraint syntax; mcgg now passes register usage information up to mcg; 
mcg can track individual hop inputs and outputs (needed for live range
analysis!); the register allocator now puts the basic blocks into the right
order in preparation for live range analysis.
 2016-10-05 22:56:25 +02:00
David Given
7a6fc7a72b Made sure that all files end in vim magic. 2016-10-05 21:07:29 +02:00
David Given
92502901a7 Better management of register data. Add struct hreg. 2016-10-05 21:00:28 +02:00
David Given
ac62c34e19 Add a pass to do critical edge splitting. 2016-10-04 23:42:00 +02:00
David Given
8fedf5a0a8 Added support for the op_bXX conditional branch instructions. 2016-10-04 23:28:16 +02:00
David Given
249855ed23 Fix the horror of the startup code; now uses getopt and stuff and the debug 
flags can be set as an option.
 2016-10-04 22:36:01 +02:00
David Given
ac063a6f54 Remove unused variable (reduce memory usage by 1/10). 2016-10-04 22:35:08 +02:00
David Given
c6f576f758 Bodge in enough phi support to let the instruction generator complete on basic 
programs.
 2016-10-04 21:58:31 +02:00
David Given
e13ff5be31 Don't allocate new vregs for REG and NOP --- a bit hacky, but suppresses stray 
movs very effectively.
 2016-10-04 21:29:03 +02:00
David Given
bd28bddb92 Massive rewrite of how emitters and the instruction selector works, after I 
realised that the existing approach wasn't working. Now, hopefully, tracks the
instruction trees generated during selection properly.
 2016-10-04 00:16:06 +02:00
David Given
68f98cbad7 Instruction selection now happens on a shadow tree, rather than on the IR tree 
itself. Currently it's semantically the same but the implementation is cleaner.
 2016-10-03 20:52:36 +02:00
David Given
288ee56203 Get quite a long way towards basic output-register equality constraints (needed 
to make special nodes like NOP work properly). Realise that the way I'm dealing
with the instruction selector is all wrong; I need to physically copy chunks of
tree to give to burg (so I can terminate them correctly).
 2016-10-02 23:25:54 +02:00
David Given
3aa30e50d1 Come up with a syntax for register constraints. 2016-10-02 21:51:25 +02:00
David Given
c079e97492 Perform SSA conversion of locals. Much, *much* better code now, at least 
inasmuch as it looks better before register allocation. Basic blocks now know
their own successors and predecessors (after a certain point in the IR
processing).
 2016-10-02 17:50:34 +02:00
David Given
79d4ab1d96 Add zrl opcode. Keep track of local sizes as well as offsets. 2016-10-02 16:08:46 +02:00
David Given
bf73fcdb64 Add inl and del opcodes. 2016-10-02 14:44:21 +02:00
David Given
b298c27c63 Refactor mcg.h as it's getting a bit big; keep track of register variables. 2016-10-02 00:30:33 +02:00
David Given
06059233da Make betterer. 2016-10-01 23:41:45 +02:00
David Given
65e75be42d Fix edge case where leftover pushes would occasionally cause infinite loops in 
the analysis.
 2016-10-01 23:41:35 +02:00
David Given
73d7e89c32 Show expression trees correctly. 2016-10-01 23:41:03 +02:00
David Given
3474e20274 Deal with malformed mes instructions emitted by ego. 2016-10-01 23:13:39 +02:00
David Given
a3cfe6047f More rigorous dealing of IR groups; no need for is_generated and is_root any 
more (but now passes are required to set IR roots properly when changing
instructions).
 2016-10-01 22:58:29 +02:00
David Given
21898f784a We're going to need some type inference after all, I think. Let's do a little 
for now and see how it goes.
 2016-10-01 19:10:22 +02:00
David Given
91e277e046 Predicates work; we now have prefers and requires clauses. Predicates must be 
functions. Not convinced that semantic types are actually working --- there are
still problems with earlier statements leaving things in the wrong registers.
 2016-10-01 13:56:52 +02:00