David Given
23c3575f0f
The register allocator now makes a spirited attempt to honour register
...
attributes when allocating. Unfortunately, backward edges don't work (because
the limited def-use chain stuff doesn't work across basic blocks). Needs more
thought.
2016-10-09 15:09:34 +02:00
David Given
637aeed70a
Only allocate an output vreg if the instruction actually wants one.
2016-10-08 12:15:21 +02:00
David Given
9ebf731335
Minor cleanup.
2016-10-08 11:07:28 +02:00
David Given
4e49830e09
Overhaul of everything phi related; critical edge splitting now happens before
...
anything SSA happens; liveness calculations now look like they might be
working.
2016-10-08 00:21:23 +02:00
David Given
88fb231d6e
Better constraint syntax; mcgg now passes register usage information up to mcg;
...
mcg can track individual hop inputs and outputs (needed for live range
analysis!); the register allocator now puts the basic blocks into the right
order in preparation for live range analysis.
2016-10-05 22:56:25 +02:00
David Given
c6f576f758
Bodge in enough phi support to let the instruction generator complete on basic
...
programs.
2016-10-04 21:58:31 +02:00
David Given
e13ff5be31
Don't allocate new vregs for REG and NOP --- a bit hacky, but suppresses stray
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movs very effectively.
2016-10-04 21:29:03 +02:00
David Given
bd28bddb92
Massive rewrite of how emitters and the instruction selector works, after I
...
realised that the existing approach wasn't working. Now, hopefully, tracks the
instruction trees generated during selection properly.
2016-10-04 00:16:06 +02:00
David Given
68f98cbad7
Instruction selection now happens on a shadow tree, rather than on the IR tree
...
itself. Currently it's semantically the same but the implementation is cleaner.
2016-10-03 20:52:36 +02:00
David Given
288ee56203
Get quite a long way towards basic output-register equality constraints (needed
...
to make special nodes like NOP work properly). Realise that the way I'm dealing
with the instruction selector is all wrong; I need to physically copy chunks of
tree to give to burg (so I can terminate them correctly).
2016-10-02 23:25:54 +02:00
David Given
a3cfe6047f
More rigorous dealing of IR groups; no need for is_generated and is_root any
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more (but now passes are required to set IR roots properly when changing
instructions).
2016-10-01 22:58:29 +02:00
David Given
91e277e046
Predicates work; we now have prefers and requires clauses. Predicates must be
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functions. Not convinced that semantic types are actually working --- there are
still problems with earlier statements leaving things in the wrong registers.
2016-10-01 13:56:52 +02:00
David Given
0d246c0d73
Much better handling of fragments (no run-time code needed to distinguish them
...
from registers) and better handling of individual hops within a paragraph ---
no more ghastly hacks to try and distinguish the input from the output.
2016-09-29 22:06:04 +02:00
David Given
4572f1b774
Actually, I don't need vregs: hops work just as well. Particularly if I
...
restructure things so that I don't need to walk the blasted ir / burg tree
every time I look at an instruction.
2016-09-27 23:38:47 +02:00
David Given
e77c5164cf
Fleshed out hops and vregs. The result is almost looking like code now ---
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uncanny.
2016-09-27 00:19:45 +02:00
David Given
c4b8e00ae2
Revamp the array module not to use nasty macros any more. Slightly more verbose
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to use, but definitely cleaner.
2016-09-26 22:48:58 +02:00
David Given
416b13fd76
Start factoring out the hardware op code.
2016-09-25 23:29:59 +02:00
David Given
39aa672422
Sort of keep track of registers and register classes. Start walking the
...
generated instruction tree --- holy cow, they look like instructions!
2016-09-25 22:17:14 +02:00
David Given
bde5792b1a
Collapse several rule arrays into one; actually generate the array properly.
2016-09-25 17:14:54 +02:00
David Given
7c028bdd45
We now record the code fragments to be emitted by each rule.
2016-09-25 00:21:46 +02:00
David Given
717b77dd0a
Instruction selection is so important the file needs a longer name.
2016-09-24 22:50:53 +02:00
