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Author SHA1 Message Date
David Given
2cc2c0ae98 Lots more opcodes. Rearrange the stack layout so that fp->ab is a fixed value 
(needed for CHAINFP and FPTOAB). Wire up lfrs to calls via a phi when
necessary, to allow call-bra-lfr chains.
 2016-10-29 11:57:56 +02:00
David Given
658db4ba71 Mangle label names (turns out that the ACK assembler can't really cope with 
labels that are the same name as instructions...).
 2016-10-27 23:17:16 +02:00
David Given
81525c0f2c Swaps work (at least for registers). More opcodes. Rearrange the stack layout 
so we can always trivially find fp, which lets CHAINFP work.
 2016-10-27 21:50:58 +02:00
David Given
b1a3d76d6f Re-re-add the type inference layer, now I know more about how things work. 
Remove that terrible float promotion code.
 2016-10-22 23:04:13 +02:00
David Given
3520704ea8 Add support for floating point constants. 2016-10-18 22:29:42 +02:00
David Given
a8ee82d197 Stop passing proc around, and use a global instead --- much cleaner. 2016-10-15 23:19:44 +02:00
David Given
7aa60a6451 Register spilling to the stack frame works, more or less. 2016-10-15 22:53:56 +02:00
David Given
9504aec2bd Function termination gets routed through an exit block; we now have prologues 
and epilogues. mcgg now exports some useful data as headers. Start factoring
out some of the architecture-specific bits into an architecture-specific file.
 2016-10-15 18:38:46 +02:00
David Given
4723a1442f Add code to remove unused phis, converting to pruned SSA form, to avoid 
confusing the register allocator later.
 2016-10-12 21:50:12 +02:00
David Given
e93c58dc8d Refactored the way hops are rendered; add support for emitting code (although 
with no prologue or epilogue yet).
 2016-10-11 00:12:11 +02:00
David Given
92bd1ac5f4 Register allocator now gets all the way through all of my test file without 
crashing (albeit with register moves and swaps stubbed out). Correct code? Who
knows.
 2016-10-10 23:19:46 +02:00
David Given
fac12aae32 Calculate phi congruency groups; use them to solve the 
importing-hreg-from-the-future problem (probably poorly).
 2016-10-09 22:04:20 +02:00
David Given
d75cc0a663 Basic register allocation works! 2016-10-08 23:32:54 +02:00
David Given
4e49830e09 Overhaul of everything phi related; critical edge splitting now happens before 
anything SSA happens; liveness calculations now look like they might be
working.
 2016-10-08 00:21:23 +02:00
David Given
ee93389c5f Refactor the cfg and dominance stuff to make it a lot nicer. 2016-10-06 21:34:21 +02:00
David Given
d20b63dc94 The register allocator is really a pass, so arrange the code like one. 2016-10-05 23:55:38 +02:00
David Given
21034c0d65 No, dammit, for register allocation I need to walk the blocks in *dominance* 
order. Since the dominance tree has changed when I fiddled with the graph, I
need to recompute it, so factor it out of the SSA pass. Code is uglier than I'd
like but at least the RET statement goes last in the generated code now.
 2016-10-05 23:52:54 +02:00
David Given
88fb231d6e Better constraint syntax; mcgg now passes register usage information up to mcg; 
mcg can track individual hop inputs and outputs (needed for live range
analysis!); the register allocator now puts the basic blocks into the right
order in preparation for live range analysis.
 2016-10-05 22:56:25 +02:00
David Given
92502901a7 Better management of register data. Add struct hreg. 2016-10-05 21:00:28 +02:00
David Given
ac62c34e19 Add a pass to do critical edge splitting. 2016-10-04 23:42:00 +02:00
David Given
288ee56203 Get quite a long way towards basic output-register equality constraints (needed 
to make special nodes like NOP work properly). Realise that the way I'm dealing
with the instruction selector is all wrong; I need to physically copy chunks of
tree to give to burg (so I can terminate them correctly).
 2016-10-02 23:25:54 +02:00
David Given
c079e97492 Perform SSA conversion of locals. Much, *much* better code now, at least 
inasmuch as it looks better before register allocation. Basic blocks now know
their own successors and predecessors (after a certain point in the IR
processing).
 2016-10-02 17:50:34 +02:00
David Given
b298c27c63 Refactor mcg.h as it's getting a bit big; keep track of register variables. 2016-10-02 00:30:33 +02:00
David Given
a3cfe6047f More rigorous dealing of IR groups; no need for is_generated and is_root any 
more (but now passes are required to set IR roots properly when changing
instructions).
 2016-10-01 22:58:29 +02:00
David Given
21898f784a We're going to need some type inference after all, I think. Let's do a little 
for now and see how it goes.
 2016-10-01 19:10:22 +02:00
David Given
4a3a9a98dc It doesn't really make a lot of sense to have BURG nonterminal names different 
to register classes, so combine them. Refactor the map code.
 2016-10-01 12:17:14 +02:00
David Given
3a973a19f3 Move fatal(), warning() and aprintf() into the new data module (because they're 
really useful).
 2016-09-30 19:10:30 +02:00
David Given
a0131fdb47 You know what, the type inference stuff is a complete red herring. What this 
actually needs is a more intelligent register allocator. So, remove the type
inference.
 2016-09-29 19:58:02 +02:00
David Given
4572f1b774 Actually, I don't need vregs: hops work just as well. Particularly if I 
restructure things so that I don't need to walk the blasted ir / burg tree
every time I look at an instruction.
 2016-09-27 23:38:47 +02:00
David Given
e77c5164cf Fleshed out hops and vregs. The result is almost looking like code now --- 
uncanny.
 2016-09-27 00:19:45 +02:00
David Given
c4b8e00ae2 Revamp the array module not to use nasty macros any more. Slightly more verbose 
to use, but definitely cleaner.
 2016-09-26 22:48:58 +02:00
David Given
cc176e5183 Keep more data around about ir instructions. Implement a half-baked type 
inference routine to propagate information about floats up the tree, so we know
whether to put floats into special registers as early as possible.
 2016-09-26 22:12:46 +02:00
David Given
416b13fd76 Start factoring out the hardware op code. 2016-09-25 23:29:59 +02:00
David Given
67eb21d428 Rename struct insn to struct em (throughout). 2016-09-25 12:29:03 +02:00
David Given
629e0ddfc6 Some instruction selection is now happening. 2016-09-24 22:46:08 +02:00
David Given
bb9aa030a5 Procedure compilation now happens after the entire EM file has been read in (so 
that we can look inside data blocks which might be defined in the future...
sigh, csa and csb). csa and csb no longer generate invalid IR.
 2016-09-24 01:04:00 +02:00
David Given
ed67d427c9 Replaced the block splicer with a trivial block eliminator (which rewrites 
jumps to blocks which contain only a jump). Don't bother storing the bb graph
in the ir nodes; we can find it on demand by walking the tree instead ---
slower, but much easier to understand and more robust. Added a terrible map
library.
 2016-09-23 23:59:15 +02:00
David Given
f8bbf9e87d Each pass now lives in its own source file; much cleaner. 2016-09-23 21:07:16 +02:00
David Given
9077baa850 Add a bodged in algorithm for converting basic block communication from stacked 
variables to SSA. Also add dead block removal and block splicing. IR code is
much better now.
 2016-09-22 23:19:29 +02:00
David Given
6a74cb2e11 Tracing cleanup. Simplified the IR code. Some more opcodes. 2016-09-22 00:15:48 +02:00
David Given
36d7d1ee4e Create hacky fake basic blocks for data fragments, used to track which 
instruction labels descriptor blocks refer to; this allows csa and csb to know
where they're going.
 2016-09-20 00:19:39 +02:00
David Given
6ce2495aeb Store the EM code up front and build the basic block graph *before* 
generating the IR code. Lots more IR code.
 2016-09-19 23:06:59 +02:00
David Given
176cd7365c Archival checking of the half-written IR treebuilder. 2016-09-18 23:24:54 +02:00
David Given
24380e2a93 Abstract out the EM reader; skeleton of the tree builder. 2016-09-18 00:02:16 +02:00