David Given
658db4ba71
Mangle label names (turns out that the ACK assembler can't really cope with
...
labels that are the same name as instructions...).
2016-10-27 23:17:16 +02:00
David Given
b1a3d76d6f
Re-re-add the type inference layer, now I know more about how things work.
...
Remove that terrible float promotion code.
2016-10-22 23:04:13 +02:00
David Given
6a23906ad8
Various bits of cleanup; we should almost be ready to try sending this to the
...
assembler soon...
2016-10-15 23:39:38 +02:00
David Given
a8ee82d197
Stop passing proc around, and use a global instead --- much cleaner.
2016-10-15 23:19:44 +02:00
David Given
7aa60a6451
Register spilling to the stack frame works, more or less.
2016-10-15 22:53:56 +02:00
David Given
9504aec2bd
Function termination gets routed through an exit block; we now have prologues
...
and epilogues. mcgg now exports some useful data as headers. Start factoring
out some of the architecture-specific bits into an architecture-specific file.
2016-10-15 18:38:46 +02:00
David Given
4723a1442f
Add code to remove unused phis, converting to pruned SSA form, to avoid
...
confusing the register allocator later.
2016-10-12 21:50:12 +02:00
David Given
e93c58dc8d
Refactored the way hops are rendered; add support for emitting code (although
...
with no prologue or epilogue yet).
2016-10-11 00:12:11 +02:00
David Given
fac12aae32
Calculate phi congruency groups; use them to solve the
...
importing-hreg-from-the-future problem (probably poorly).
2016-10-09 22:04:20 +02:00
David Given
d75cc0a663
Basic register allocation works!
2016-10-08 23:32:54 +02:00
David Given
4e49830e09
Overhaul of everything phi related; critical edge splitting now happens before
...
anything SSA happens; liveness calculations now look like they might be
working.
2016-10-08 00:21:23 +02:00
David Given
ee93389c5f
Refactor the cfg and dominance stuff to make it a lot nicer.
2016-10-06 21:34:21 +02:00
David Given
d20b63dc94
The register allocator is really a pass, so arrange the code like one.
2016-10-05 23:55:38 +02:00
David Given
88fb231d6e
Better constraint syntax; mcgg now passes register usage information up to mcg;
...
mcg can track individual hop inputs and outputs (needed for live range
analysis!); the register allocator now puts the basic blocks into the right
order in preparation for live range analysis.
2016-10-05 22:56:25 +02:00
David Given
ac62c34e19
Add a pass to do critical edge splitting.
2016-10-04 23:42:00 +02:00
David Given
c079e97492
Perform SSA conversion of locals. Much, *much* better code now, at least
...
inasmuch as it looks better before register allocation. Basic blocks now know
their own successors and predecessors (after a certain point in the IR
processing).
2016-10-02 17:50:34 +02:00
David Given
a3cfe6047f
More rigorous dealing of IR groups; no need for is_generated and is_root any
...
more (but now passes are required to set IR roots properly when changing
instructions).
2016-10-01 22:58:29 +02:00
David Given
21898f784a
We're going to need some type inference after all, I think. Let's do a little
...
for now and see how it goes.
2016-10-01 19:10:22 +02:00
David Given
a0131fdb47
You know what, the type inference stuff is a complete red herring. What this
...
actually needs is a more intelligent register allocator. So, remove the type
inference.
2016-09-29 19:58:02 +02:00
David Given
c4b8e00ae2
Revamp the array module not to use nasty macros any more. Slightly more verbose
...
to use, but definitely cleaner.
2016-09-26 22:48:58 +02:00
David Given
cc176e5183
Keep more data around about ir instructions. Implement a half-baked type
...
inference routine to propagate information about floats up the tree, so we know
whether to put floats into special registers as early as possible.
2016-09-26 22:12:46 +02:00
David Given
629e0ddfc6
Some instruction selection is now happening.
2016-09-24 22:46:08 +02:00
David Given
bb9aa030a5
Procedure compilation now happens after the entire EM file has been read in (so
...
that we can look inside data blocks which might be defined in the future...
sigh, csa and csb). csa and csb no longer generate invalid IR.
2016-09-24 01:04:00 +02:00
