Tests pass if one edits the top build.lua to uncomment "qemuppc" from
both vars.plats and vars.plats_with_tests, and one leaves mcg in
plat/qemuppc/descr.
Add or correct some EM instructions in treebuilder.c:
- "lof", "stf": handle negative offsets in load() and store().
- "cuu": add using IR_FROMUI.
- "lim", "sim": keep an entire word in ".ignmask", to be compatible
with mach/powerpc/libem/trp.s and ncg. We also keep a word in
".ignmask" in ncg for both i386 and m68020.
- "trp": pass trap number in register. See comment in
helper_function_with_arg().
- "sig": push the old value of .trppc on the stack.
- "and ?", "ior ?", "xor ?", "com ?", "cms ?", "set ?", "inn ?":
connect to helper functions in libem.
- "blm", "bls": drop call to memmove() and use new helper ".bls4",
because tests/plat/structcopy_e.c can't call memmove().
- "xor s", "cms s": if s is large, fall back on helper function.
- "rol", "ror": add by decomposing each rotate into 4 IR ops.
- "rck s", "bls s": make fatal unless s is word size.
- "loi": push multiple loads in the correct order.
- "dup s", "exg s": if s is large, fall back on helper.
- "dus": add using new helper ".dus4".
- "lxl", "lxa": follow the static chain, not the dynamic chain.
- "lor 1": materialise the stack before pushing the stack pointer.
- "lor 2", "str 2": make fatal.
- "los", "sts": drop calls to memcpy() and use helpers ".los4" and
and ".sts4", so lang/m2/libm2/LtoUset.e starts working.
- "gto": correctly read descriptor.
Change mach/powerpc/mcg/table:
- ANY.L: add for "asp -8".
- LOAD.L: work around register corruption.
- COMPAREUL.I: add for "cms 8".
possible values. Add the PowerPC ncg and mcg backend support to let the test
actually run, including modifying a bunch of PowrePC libem functions so that
they can be called from both ncg and mcg.
corresponding invocation in the ncg table so the same helpers can be used for
both mcg and ncg. Add a new IR opcode, FARJUMP, which jumps to a helper
function but saves volatile registers.
and epilogues. mcgg now exports some useful data as headers. Start factoring
out some of the architecture-specific bits into an architecture-specific file.
jumps to blocks which contain only a jump). Don't bother storing the bb graph
in the ir nodes; we can find it on demand by walking the tree instead ---
slower, but much easier to understand and more robust. Added a terrible map
library.
