Commit graph

2370 commits

Author SHA1 Message Date
George Koehler cfbc537959 In powerpc ncg, add a speed hack for sti 8.
ncg is too slow with this many registers.  A stack pattern "with GPR
GPR GPR" or "with REG REG REG" takes too long to pick registers,
causing ncg 8 to take about 2 seconds on each sti 8.  I introduce
REG_PAIR and there are only 4 such pairs.

For programs that use sti 8 (including C programs that copy 8-byte
structs), this speed hack improves the ncg run from several seconds to
almost instantaneous.

Also add a few COMMENT(...) lines in stacking rules.
2016-10-17 20:31:59 -04:00
David Given 938fb8c2fc Lots more opcodes. 2016-10-18 00:31:26 +02:00
David Given 4a093b9eba Add li and mr pseudoinstructions. 2016-10-18 00:21:32 +02:00
George Koehler c7b68033ef Add costs to powerpc instructions.
Also show how andi., andis., or., set condition codes.
2016-10-17 14:57:21 -04:00
George Koehler f33b30ed3c Rewrite .fif8 to avoid powerpc64 fctid
This fixes the SIGILL (illegal instruction) in startrek when firing
phasers.  The 32-bit processors in my PowerPC Mac and in QEMU don't
have fctid, a 64-bit instruction.

I got the idea from mach/proto/fp/fif8.c to extract the exponent,
clear some bits to get an integer, then subtract the integer from
the original value to get the fraction.
2016-10-17 00:39:59 -04:00
George Koehler e2ccc8f942 Add "kills MEMORY" to powerpc sti rules.
Adjust some of the loi rules (and associated moves) so we can identify
the tokens that must be in MEMORY.

With this commit, I can navigate the Enterprise even if I comment out
my work-around from e22c888.
2016-10-16 18:13:39 -04:00
David Given 5f0164db62 Bolt mcg into the PowerPC backend. It doesn't build yet, but it is generating
*some* code.
2016-10-17 00:06:06 +02:00
David Given d539389e81 Merge in the unfinished PowerPC branch. 2016-10-16 22:38:27 +02:00
David Given 1e17921208 Implement saving of dirty registers onto the stack. 2016-10-16 22:37:42 +02:00
George Koehler 19f0eb86a4 Remove IND_LABEL_W and IND_LABEL_D
Because li32 always loads a label into a GPR, it is sufficient to
coerce LABEL to REG, then use IND_RC_W or IND_RC_D for indirection
through the label.
2016-10-16 16:33:24 -04:00
George Koehler 5b5f774a64 Simplify moves to and from IND_RC_*
Now that SUM_RC always has a signed 16-bit constant, it happens that
the various IND_RC_* tokens also have a signed 16-bit constant, so
we no longer need to touch the scratch register.
2016-10-16 16:02:25 -04:00
George Koehler 7c64dab491 Refactor how powerpc ncg pushes constants.
When loc (load constant) pushes a constant, it now checks the value of
the constant and pushes any of 7 tokens.  These tokens allow stack
patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned
integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other
interesting forms of constants.

Use the new constant tokens in the rules for adi, sbi, and, ior, xor.
Adjust a few other rules to understand the new tokens.

Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC
each have an unsigned 16-bit constant.  The moves from SUM_RC, OR_RC,
XOR_RC to GPR no longer touch the scratch register, because the
constant is not too big.
2016-10-16 13:58:54 -04:00
George Koehler baa152217e Remove unused parts of mach/powerpc/ncg/table
Remove unused tokens GPRINDIRECTLO, HILABEL, LOLABEL, LABELI.  Also
remove an #if 0 ... #endif group of patterns.
2016-10-15 20:00:48 -04:00
David Given 6a23906ad8 Various bits of cleanup; we should almost be ready to try sending this to the
assembler soon...
2016-10-15 23:39:38 +02:00
David Given 286435a2ed Oops, forgot to add the output option spec to the string! 2016-10-15 23:34:54 +02:00
David Given b36897c299 References to the stack frame are now rendered properly. 2016-10-15 23:33:30 +02:00
David Given a8ee82d197 Stop passing proc around, and use a global instead --- much cleaner. 2016-10-15 23:19:44 +02:00
David Given 7aa60a6451 Register spilling to the stack frame works, more or less. 2016-10-15 22:53:56 +02:00
David Given 0eb32e7553 Fix yet another bug to do with IR register outputs. 2016-10-15 19:14:25 +02:00
David Given 9504aec2bd Function termination gets routed through an exit block; we now have prologues
and epilogues. mcgg now exports some useful data as headers. Start factoring
out some of the architecture-specific bits into an architecture-specific file.
2016-10-15 18:38:46 +02:00
David Given 5ad3aa8595 Add a pile of new instructions used by Pascal; I'm going to need to think about
how locals and the local base are handled.
2016-10-15 13:07:59 +02:00
David Given 358c44de35 Bytes were sometimes failing to be sign extended correctly. 2016-10-15 12:11:40 +02:00
David Given 517120d0fb Allow asm names for registers which are different from the friendly names shown
in the tracing (because PowerPC register names are just numbers).
2016-10-15 11:42:47 +02:00
David Given b2ddf12473 Some more opcodes. 2016-10-15 11:22:40 +02:00
George Koehler 29cb008faa In powerpc table, fix macros los() and his().
Change the operator in his() from a - minus to a + plus.  When los(n)
becomes negative, then his(n) needs to add 0x10000, not subtract it.

Also change los(n) to do the sign extension, because smalls(los(n))
should be true, not false.

Also change hi(n) and lo(n) to wrap n in parentheses, as (n), because
these are macros and n might still contain operators.
2016-10-14 23:59:26 -04:00
David Given bb17aea73a You can now mark a register as corrupting a certain register class; calls work,
or at least look like they work. The bad news is that the register allocator
has a rare talent for putting things in the wrong register.
2016-10-15 01:15:08 +02:00
David Given 886adb86d7 Log empty hops. 2016-10-14 23:19:25 +02:00
David Given 4f2177e41f Reworked loads and stores; it's now *different*, maybe not better. 2016-10-14 23:19:02 +02:00
David Given a63052427e Factor out the register allocation routines to make them easier to deal with. 2016-10-14 23:17:06 +02:00
David Given bb53a7fb51 Fix stupid issue where hop output registers were being overwritten, leading to
invalid SSA form.
2016-10-14 23:12:29 +02:00
David Given 98fe70a7de Output register equality constraints work. 2016-10-14 22:17:02 +02:00
David Given 216ff5cc43 Make loads and stores in the table nicer; fix a place where it looked like it
was working but only accidentally.
2016-10-12 23:12:53 +02:00
David Given f06b51c981 Keep track of register types as well as attributes --- the type being how we
find new registers when evicting values. Input constraints work (they were
being ignored before). Various bug fixing so they actually work.
2016-10-12 22:58:46 +02:00
David Given 4723a1442f Add code to remove unused phis, converting to pruned SSA form, to avoid
confusing the register allocator later.
2016-10-12 21:50:12 +02:00
David Given df239b3f90 Don't allow the same IR to be added to the sequence list more than once
(sometimes happens because op_dup, but makes no sense).
2016-10-12 00:45:36 +02:00
David Given 96dffd2007 Clean up the allocator a bit, in preparation for making it lots more
complicated; no semantic changes.
2016-10-11 23:17:30 +02:00
David Given 668cccdff1 A few more opcodes. 2016-10-11 00:29:18 +02:00
David Given 2be1c51885 A little fiddling with store instructions. The PowerPC is not friendly to
iburg.
2016-10-11 00:23:35 +02:00
David Given e93c58dc8d Refactored the way hops are rendered; add support for emitting code (although
with no prologue or epilogue yet).
2016-10-11 00:12:11 +02:00
David Given 92bd1ac5f4 Register allocator now gets all the way through all of my test file without
crashing (albeit with register moves and swaps stubbed out). Correct code? Who
knows.
2016-10-10 23:19:46 +02:00
David Given a4d06d1795 D'oh, need multiple passes over the edge splitter in order to properly find all
cases.
2016-10-10 23:18:37 +02:00
David Given fac12aae32 Calculate phi congruency groups; use them to solve the
importing-hreg-from-the-future problem (probably poorly).
2016-10-09 22:04:20 +02:00
David Given 23c3575f0f The register allocator now makes a spirited attempt to honour register
attributes when allocating. Unfortunately, backward edges don't work (because
the limited def-use chain stuff doesn't work across basic blocks). Needs more
thought.
2016-10-09 15:09:34 +02:00
David Given 38de688c5a Floating point promotion was broken since the IR float change. Fix. 2016-10-09 15:08:03 +02:00
David Given 36cddd6afb Add some more opcodes; rearrange the registers to be more PowerPC-friendly. 2016-10-09 14:45:13 +02:00
David Given cfe5312fcc Predicates can now take numeric arguments. The PowerPC predicates have been
turned into generic ones (as they'll be useful everywhere). Node arguments for
predicates require the '%' prefix for consistency. Hex numbers are permitted.
2016-10-09 12:32:36 +02:00
David Given d75cc0a663 Basic register allocation works! 2016-10-08 23:32:54 +02:00
David Given 637aeed70a Only allocate an output vreg if the instruction actually wants one. 2016-10-08 12:15:21 +02:00
David Given 2198db69b1 Instruction predicates work now. 2016-10-08 11:35:33 +02:00
David Given 9ebf731335 Minor cleanup. 2016-10-08 11:07:28 +02:00
David Given 9db902314b Fix bug where pushes were being placed in the wrong blocks. 2016-10-08 10:21:24 +02:00
George Koehler 65c2a8a0ae Remove stackadjust and stackoffset() from ncg.
This feature has never been used since its introduction, more than 3
years ago, in David Given's commit c93cb69 of May 8, 2013.  The commit
was for "PowerPC and M68K work".  I am not undoing the entire commit.
I am only removing the stackadjust and stackoffset() feature.

This commit removes the feature from my branch kernigh-linuxppc.  This
removal includes the mach/proto/ncg parts.  The default branch already
removed most of the feature, but kept the mach/proto/ncg parts.  That
removal happened in commit 81778b6 of May 13, 2013 (which was a merge;
git diff af0dede 81778b6).  The branch dtrg-experimental-powerpc
merged the default branch but without the removal.  That merge was
commit 4703db0f of Sep 15, 2016 (git diff 8c94b13 4703db0).  My branch
kernigh-linuxppc is off branch dtrg-experimental-powerpc, so I can no
longer get the removal by merging default.

David Given described the stackadjust feature in
  https://sourceforge.net/p/tack/mailman/message/30814691/

The instruction stackadjust would add a value to the offset, and the
function stackoffset() would return this offset.  One would use this
to track sp - fp, then omit the frame pointer by not keeping fp in a
register.
2016-10-07 20:52:13 -04:00
David Given 4e49830e09 Overhaul of everything phi related; critical edge splitting now happens before
anything SSA happens; liveness calculations now look like they might be
working.
2016-10-08 00:21:23 +02:00
George Koehler 409ba7fb1b Remove most of GPRE from mach/powerpc/ncg/table
We only need GPRE in a few places where we write {GPRE, regvar(...)}
because ncgg can't parse plain regvar(...).  In all other places, a
plain GPR works.

Also remove gpr_gpr_gpr and a few other unused and fake instructions
from the list of instructions.
2016-10-06 22:59:27 -04:00
George Koehler 7cccd88b71 Rename SCRATCH to RSCRATCH. Never stack RSCRATCH nor FSCRATCH.
Rename the scratch gpr (currently r11) from SCRATCH to RSCRATCH so I
can search for RSCRATCH without finding FSCRATCH.  I also want to
avoid confusion with the SCRATCH keyword of the old code generator (cg
which came before ncg).

Change the stacking rules to prevent stacking of RSCRATCH or FSCRATCH
or any other GPR or FPR that isn't an allocatable REG or FREG.  Then
ncgg rejects any rule that tries to stack a GPR or FPR, so change such
rules to stack a REG or FREG.
2016-10-06 20:47:42 -04:00
David Given ee93389c5f Refactor the cfg and dominance stuff to make it a lot nicer. 2016-10-06 21:34:21 +02:00
David Given d20b63dc94 The register allocator is really a pass, so arrange the code like one. 2016-10-05 23:55:38 +02:00
David Given 87e004e4a9 Warning fix. 2016-10-05 23:55:04 +02:00
David Given 21034c0d65 No, dammit, for register allocation I need to walk the blocks in *dominance*
order. Since the dominance tree has changed when I fiddled with the graph, I
need to recompute it, so factor it out of the SSA pass. Code is uglier than I'd
like but at least the RET statement goes last in the generated code now.
2016-10-05 23:52:54 +02:00
David Given d95c75dfd7 Allowing an input filename on the command line makes debuggers happy. (Then we
don't need to redirect stdin.)
2016-10-05 23:24:29 +02:00
David Given 88fb231d6e Better constraint syntax; mcgg now passes register usage information up to mcg;
mcg can track individual hop inputs and outputs (needed for live range
analysis!); the register allocator now puts the basic blocks into the right
order in preparation for live range analysis.
2016-10-05 22:56:25 +02:00
David Given 7a6fc7a72b Made sure that all files end in vim magic. 2016-10-05 21:07:29 +02:00
David Given 92502901a7 Better management of register data. Add struct hreg. 2016-10-05 21:00:28 +02:00
David Given ac62c34e19 Add a pass to do critical edge splitting. 2016-10-04 23:42:00 +02:00
David Given 8fedf5a0a8 Added support for the op_bXX conditional branch instructions. 2016-10-04 23:28:16 +02:00
David Given 249855ed23 Fix the horror of the startup code; now uses getopt and stuff and the debug
flags can be set as an option.
2016-10-04 22:36:01 +02:00
David Given ac063a6f54 Remove unused variable (reduce memory usage by 1/10). 2016-10-04 22:35:08 +02:00
David Given c6f576f758 Bodge in enough phi support to let the instruction generator complete on basic
programs.
2016-10-04 21:58:31 +02:00
David Given e13ff5be31 Don't allocate new vregs for REG and NOP --- a bit hacky, but suppresses stray
movs very effectively.
2016-10-04 21:29:03 +02:00
David Given bd28bddb92 Massive rewrite of how emitters and the instruction selector works, after I
realised that the existing approach wasn't working. Now, hopefully, tracks the
instruction trees generated during selection properly.
2016-10-04 00:16:06 +02:00
David Given 68f98cbad7 Instruction selection now happens on a shadow tree, rather than on the IR tree
itself. Currently it's semantically the same but the implementation is cleaner.
2016-10-03 20:52:36 +02:00
David Given 288ee56203 Get quite a long way towards basic output-register equality constraints (needed
to make special nodes like NOP work properly). Realise that the way I'm dealing
with the instruction selector is all wrong; I need to physically copy chunks of
tree to give to burg (so I can terminate them correctly).
2016-10-02 23:25:54 +02:00
David Given 3aa30e50d1 Come up with a syntax for register constraints. 2016-10-02 21:51:25 +02:00
David Given c079e97492 Perform SSA conversion of locals. Much, *much* better code now, at least
inasmuch as it looks better before register allocation. Basic blocks now know
their own successors and predecessors (after a certain point in the IR
processing).
2016-10-02 17:50:34 +02:00
David Given 79d4ab1d96 Add zrl opcode. Keep track of local sizes as well as offsets. 2016-10-02 16:08:46 +02:00
David Given bf73fcdb64 Add inl and del opcodes. 2016-10-02 14:44:21 +02:00
David Given b298c27c63 Refactor mcg.h as it's getting a bit big; keep track of register variables. 2016-10-02 00:30:33 +02:00
David Given 06059233da Make betterer. 2016-10-01 23:41:45 +02:00
David Given 65e75be42d Fix edge case where leftover pushes would occasionally cause infinite loops in
the analysis.
2016-10-01 23:41:35 +02:00
David Given 73d7e89c32 Show expression trees correctly. 2016-10-01 23:41:03 +02:00
David Given 3474e20274 Deal with malformed mes instructions emitted by ego. 2016-10-01 23:13:39 +02:00
David Given a3cfe6047f More rigorous dealing of IR groups; no need for is_generated and is_root any
more (but now passes are required to set IR roots properly when changing
instructions).
2016-10-01 22:58:29 +02:00
David Given 21898f784a We're going to need some type inference after all, I think. Let's do a little
for now and see how it goes.
2016-10-01 19:10:22 +02:00
David Given 91e277e046 Predicates work; we now have prefers and requires clauses. Predicates must be
functions. Not convinced that semantic types are actually working --- there are
still problems with earlier statements leaving things in the wrong registers.
2016-10-01 13:56:52 +02:00
David Given 4a3a9a98dc It doesn't really make a lot of sense to have BURG nonterminal names different
to register classes, so combine them. Refactor the map code.
2016-10-01 12:17:14 +02:00
George Koehler ce5faba919 Remove .linenumber and .filename; use hol0 and hol0+4.
We need this because some .e files in lang/ are using 'loe 0' and 'lae
4' to load the line number from hol0 and filename from hol0+4.
2016-09-30 13:40:36 -04:00
David Given 3a973a19f3 Move fatal(), warning() and aprintf() into the new data module (because they're
really useful).
2016-09-30 19:10:30 +02:00
George Koehler e22c8881e7 Add a rule for sdl ldl $1==$2 to work around a bug.
In our powerpc table, sdl fails to kill the old value of the local.
This is a bug, because a later ldl can load the old value instead of
the newly stored value.  By rewriting "sdl 0" "ldl 0" as "dup 8" "sdl
0", the newly added rule works around the bug, but only when the ldl
is immediately after the sdl.

This rule improves code that uses double-precision floating point.
The output of printf("%f", 6.0) in C changes from all zero digits to
"6000000" but still doesn't print the decimal point.  The result of
atof("-123.456") becomes correct.  In startrek, I can now move the
Enterprise, but I still can't fire phasers without crashing the game.

We already have a rule for stl lol $1==$2.  We had two copies of the
rule, so I am deleting the second copy.
2016-09-30 11:50:50 -04:00
David Given 0d246c0d73 Much better handling of fragments (no run-time code needed to distinguish them
from registers) and better handling of individual hops within a paragraph ---
no more ghastly hacks to try and distinguish the input from the output.
2016-09-29 22:06:04 +02:00
George Koehler 6ae415d48b Rewrite fef 8 in powerpc assembly.
In EM, fef splits a float into exponent and fraction.  The old C code,
given an infinite float, got stuck in an infinite loop.  The new
assembly code doesn't loop; it extracts the IEEE exponent.
2016-09-29 15:52:54 -04:00
David Given a0131fdb47 You know what, the type inference stuff is a complete red herring. What this
actually needs is a more intelligent register allocator. So, remove the type
inference.
2016-09-29 19:58:02 +02:00
George Koehler a71eee3914 For "pat ass", move fake stack to real stack before adjusting SP.
This fixes code that tried to "addi SP, SP, 4" to drop a value that
was in a register, not on the real stack.

Add a rule to optimize "asp 4" (which becomes "loc 4" "ass") when
the value being dropped is already in a GPR.
2016-09-28 00:13:35 -04:00
David Given 4572f1b774 Actually, I don't need vregs: hops work just as well. Particularly if I
restructure things so that I don't need to walk the blasted ir / burg tree
every time I look at an instruction.
2016-09-27 23:38:47 +02:00
George Koehler 1e3dde915a Remove the "invalid" stacking rule.
When ncg fell back on this rule, it did emit the string "invalid" in
the assembly code and caused a syntax error in the assembler.

Adjust the stacking rules so we can stack LOCAL, CONST, and LABEL
without falling back on the "invalid" rule, and so we can stack them
when we have no free register except the scratch register.
2016-09-27 16:46:11 -04:00
David Given e77c5164cf Fleshed out hops and vregs. The result is almost looking like code now ---
uncanny.
2016-09-27 00:19:45 +02:00
David Given f552c9c7c6 Move map into the data module. 2016-09-26 23:03:04 +02:00
David Given c4b8e00ae2 Revamp the array module not to use nasty macros any more. Slightly more verbose
to use, but definitely cleaner.
2016-09-26 22:48:58 +02:00
David Given 3671892c34 Move the array library into the data module. 2016-09-26 22:24:49 +02:00
David Given cc176e5183 Keep more data around about ir instructions. Implement a half-baked type
inference routine to propagate information about floats up the tree, so we know
whether to put floats into special registers as early as possible.
2016-09-26 22:12:46 +02:00
David Given 416b13fd76 Start factoring out the hardware op code. 2016-09-25 23:29:59 +02:00