This provides and, ior, xor, com, zer, set, cms when defined($1) and
ior, set when !defined($1). I don't provide the other operations
!defined($1) because our Modula-2 compiler hasn't used them.
I wrote a Modula-2 example in
https://gist.github.com/kernigh/add79662bb3c63ffb7c46d01dc8ae788
Put a dummy comment in mach/powerpc/libem/build.lua so git checkout
will touch that file. Without the touch, the build system doesn't see
the new *.s files.
We only implement 'los 4', 'sts 4', 'cmi 4', 'cmu 4', not for sizes
other than 4. Add clause $1==4.
We only implement inn when defined($1).
The rule for aar needs 'kills ALL' because it kills many registers,
like other rules that call libem.
This allows 'move {CONST, $1}, R3' with a small enough $1 to emit one
instruction (addi) instead of two instructions (addis, ori). The
CONST token confusingly isn't in the CONST_ALL set.
The spec says, "ASS w: Adjust the stack pointer by w-byte integer".
The w argument "can either be given as argument or on top of the
stack." Therefore, 'ass 4' would pop the 4-byte integer from the
stack, but 'ass' would pop the size w from the stack, then pop the
w-byte integer.
PowerPC ncg wrongly implemented 'ass' as if it was 'ass 4'. Fix it to
accept only 'ass 4'.
These instructions would load or store the EM heap pointer. They
don't work. Programs must use brk() or sbrk() in libsys.
The last file to use 'lor 2' and 'str 2' was lang/pc/libpc/sav.e in
the Pascal library. Commit c084f9f deleted the file, so we no longer
need rules 'lor 2' or 'str 2' to build the ACK.
PowerPC has a few hundred special-purpose registers. The assembler
had only accepted the names "xer", "lr", "ctr". Most programs use
only those three SPRs. If I add more names, they would almost never
get used, and they might conflict with labels.
I want to use "mfspr r3, 0x3f0" and "mtspr 0x3f0, r3" in
plat/qemu/boot.s to access register hid0 from supervisor mode.
corresponding invocation in the ncg table so the same helpers can be used for
both mcg and ncg. Add a new IR opcode, FARJUMP, which jumps to a helper
function but saves volatile registers.
occasionally the first hop of a block would try to rearrange its registers (due
to evicted throughs), resulting in the phi moves copying values into the wrong
registers.
register 'type'; now use int/float/long/double throughout to identify
registers. Lots of register allocator tweaks and table bugfixes --- we now get
through the dreading Mathlib.mod!
This would have happened later, if f14 to f31 became regvar (like r13
to r31 are now). I am doing it now because ncg is too slow for rules
"with FREG FREG uses FREG". We use such rules for adf 8 and other EM
instructions that operate on 2 floats. Like my last commit cfbc537,
this commit speeds ncg by removing choices for register allocation.
ncg is too slow with this many registers. A stack pattern "with GPR
GPR GPR" or "with REG REG REG" takes too long to pick registers,
causing ncg 8 to take about 2 seconds on each sti 8. I introduce
REG_PAIR and there are only 4 such pairs.
For programs that use sti 8 (including C programs that copy 8-byte
structs), this speed hack improves the ncg run from several seconds to
almost instantaneous.
Also add a few COMMENT(...) lines in stacking rules.
This fixes the SIGILL (illegal instruction) in startrek when firing
phasers. The 32-bit processors in my PowerPC Mac and in QEMU don't
have fctid, a 64-bit instruction.
I got the idea from mach/proto/fp/fif8.c to extract the exponent,
clear some bits to get an integer, then subtract the integer from
the original value to get the fraction.
Adjust some of the loi rules (and associated moves) so we can identify
the tokens that must be in MEMORY.
With this commit, I can navigate the Enterprise even if I comment out
my work-around from e22c888.
Because li32 always loads a label into a GPR, it is sufficient to
coerce LABEL to REG, then use IND_RC_W or IND_RC_D for indirection
through the label.
Now that SUM_RC always has a signed 16-bit constant, it happens that
the various IND_RC_* tokens also have a signed 16-bit constant, so
we no longer need to touch the scratch register.
When loc (load constant) pushes a constant, it now checks the value of
the constant and pushes any of 7 tokens. These tokens allow stack
patterns to recognize 16-bit signed integers (CONST2), 16-bit unsigned
integers (UCONST2), multiples of 0x10000 (CONST_HZ), and other
interesting forms of constants.
Use the new constant tokens in the rules for adi, sbi, and, ior, xor.
Adjust a few other rules to understand the new tokens.
Require that SUM_RC has a signed 16-bit constant, and OR_RC and XOR_RC
each have an unsigned 16-bit constant. The moves from SUM_RC, OR_RC,
XOR_RC to GPR no longer touch the scratch register, because the
constant is not too big.
and epilogues. mcgg now exports some useful data as headers. Start factoring
out some of the architecture-specific bits into an architecture-specific file.
Change the operator in his() from a - minus to a + plus. When los(n)
becomes negative, then his(n) needs to add 0x10000, not subtract it.
Also change los(n) to do the sign extension, because smalls(los(n))
should be true, not false.
Also change hi(n) and lo(n) to wrap n in parentheses, as (n), because
these are macros and n might still contain operators.
