.\" $Header$
.TH NS_AS 6ACK
.ad
.SH NAME
ns_as \- National Semiconductor 16032 assembler/linker
.SH SYNOPSIS
~em/lib/ns/as [options] argument ...
.SH DESCRIPTION
The assembler for the National Semiconductor 16032 is based
on the universal assembler \fIuni_ass\fP(VI). It is an assembler generating
relocatable object code in \fIack.out\fP(5) format.
The mnemonics for the instructions are taken from the NS-16000
Programmers Reference Manual.
The syntax of the instruction operands is similar to the syntax used
in that manual,
although the meaning is sometimes quite different.
The cross assembler issued by National Semiconductor
associates a type (sb,..) with each symbol
and automatically generates sb offset mode for symbols of type sb.
This assembler does not record the types,
each symbol simply produces an untyped value.
.sp 1
The possible operands are:
.IP "general registers
These are called r0, r1, r2, r3, r4, r5, r6 and r7.
The symbol REG is used to indicate use of any of these 8 registers
in other operands.
.IP "floating point registers
These are called f0, f1, f2, f3, f4, f5, f6 and f7.
.IP "dedicated registers
All types of dedicated registers can be used with the appropriate instructions.
Examples: sb, fp, intbase, ptb1.
.IP expr(REG)
register relative
.IP expr(fp)
frame pointer relative
.IP expr(sb)
static base relative
.IP expr(sp)
stack pointer relative
.IP expr(pc)
program counter relative,
the expression indicates a location in memory from which the current value
of '.' is subtracted by the assembler.
E.g. "movw label(pc),r0; label: .word ..." moves the contents of the word
at \fIlabel\fP to r0.
.IP expr(expr(fb))
.IP expr(expr(sb))
.IP expr(expr(sp))
memory relative
.IP @expr
absolute
.IP external(expr)+expr
external
.IP tos
top of stack.
.PD 0
.sp 1
.PP
Usage of the scaled index operands is allowed.
.br
The convention used to indicate offset length by appending :B, :W or :D
to offsets is not implemented.
The assembler tries to find out the minimal size needed for any constant
in an operand of the instruction placed in the text segment.
Offsets in instructions outside \fI.text\fP are always four bytes.
.PP
All special operands, e.g. register list, configuration list, have
the same format as in the Programmers Reference Manual.
.PP
Whenever possible the assembler automatically uses the short(quick) opcodes for
jsr(jsb), jump(br), add(addq), cmp(cmpq) and mov(movq).
.SH BUGS
The data types floating and packed-decimal are not supported.
.br
Initialization of floating-point numbers is not possible.
.br
The mnemonics of the slave processor instructions are poorly documented,
the format of the NS-16032S-6 data sheet is used.
.br
The documentation gave contradictory information on the format
of a few instructions.
.IP -
Three different schemes are presented for the encoding
of the last operand of the block instructions.
.IP -
Two different values are specified for
the encoding of the msr register in smr and lmr instructions.
.IP -
Two different possibilities are given for the encoding of
the instructions movsu and movus.
.SH "SEE ALSO"
uni_ass(VI)
ack(1),
ack.out(5),
.br
NS 16000 Programmers Reference Manual. Publ. no. 420306565-001PB
.br
NS16032S-6, NS16032S-4 High Performance Microprocessors, november 1982
.br
publ. no. 420306619-002A.
.PD 0
.SH AUTHOR
Ed Keizer, Vrije Universiteit