.\" $Header$
.TH I86_AS 6 "$Revision$"
.ad
.SH NAME
i86_as \- assembler for Intel 8086
.SH SYNOPSIS
~em/lib.bin/i86/as [options] argument ...
.SH DESCRIPTION
This assembler is made with the general framework
described in \fIuni_ass\fP(6). It is an assembler generating relocatable
object code in \fIack.out\fP(5) format.
.SH SYNTAX
.IP segments
An address on the Intel 8086 consists of two pieces:
a segment number and an offset. A memory address is computed as
the segment number shifted left 4 bits + the offset.
Assembly language addresses only give the offset, with the exception of
the address of an inter-segment jump or call (see \fIaddressing modes\fP
below).
.IP registers
The Intel 8086 has the following 16-bit registers:
.br
Four general registers: ax (accumulator), bx (base), cx (count), and dx (data).
The upper halves and lower halves of these registers are separately
addressable as ah, bh, ch, dh, and al, bl, cl, dl respectively.
.br
Two pointer registers: sp (stack pointer) and bp (base pointer).
.br
Two index registers: si (source index) and di (destination index).
.br
Four segment registers: cs (code), ds (data), ss (stack), and es (extra).
.IP "addressing modes"
.nf
.ta 8n 16n 24n 32n 40n 48n
syntax		meaning

expr		the value of \fIexpr\fP is immediate data or
		an address offset. There is no special
		notation for immediate data.

register	one of the aforementioned general registers
		or their upper or lower halves, or one of the
		four segment registers.

(expr)		the value of expr is the address of the operand.

(reg)
expr (reg)	the value of \fIexpr\fP (if present) + the contents of
		\fIreg\fP (which must be a pointer or an index register)
		is the address of the operand.

(preg) (ireg)
expr (preg) (ireg)
		the value of \fIexpr\fP (if present) + the contents of
		\fIpreg\fP (which must be a pointer register) + the
		contents of \fIireg\fP (which must be an index register)
		is the address of the operand.

The next addressing mode is only allowed with the instructions
"callf" or "jmpf".

expr : expr	the value of the first \fIexpr\fP is a segment number,
		the value of the second \fIexpr\fP is an address offset.
		The (absolute) address of the operand is computed
		as described above.
.fi

.IP instructions
Each time an address is computed the processor decides which segment register
to use. You can override the processor's choice by prefixing the instruction
with one of eseg, cseg, sseg, or dseg; these prefixes indicate that the
assembler should choose es, cs, ss, or ds instead.
.br
Example: 
.ti +8
dseg movs
.SH "SEE ALSO"
uni_ass(6),
ack(1),
ack.out(5),
.br
MCS-86 assembly language reference manual, 1978, Intel Corporation
.SH EXAMPLE
.nf
.ta 8n 16n 24n 32n 40n 48n
An example of Intel 8086 assembly language:

	.sect .text
	_panic:
		push	bp
		mov	bp,sp
	.sect .data
	_35:
	.data2	24944
	.data2	26990
	.data2	14947
	.data2	32
	.sect .text
	call _disable
	mov ax,_35
	push ax
	call _str
	pop si
	push 4(bp)
	call _str
	pop si
	call _nlcr
	call _exit
	mov sp,bp
	pop bp
	ret
	.extern _nopanic
	_nopanic:
		push	bp
		mov	bp,sp
	.sect .data
	_38:
	.data2	28526
	.data2	24944
	.data2	26990
	.data2	14947
	.data2	32
	.sect .text
	mov ax,_38
	push ax
	call _str
	pop si
	push 4(bp)
	call _str
	pop si
	push 6(bp)
	call _octal
	pop si
	mov sp,bp
	pop bp
	ret
.fi