687 lines
14 KiB
C
687 lines
14 KiB
C
/* $Id$ */
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/*
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* (c) copyright 1987 by the Vrije Universiteit, Amsterdam, The Netherlands.
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* See the copyright notice in the ACK home directory, in the file "Copyright".
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*/
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/*
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* Motorola 68020 auxiliary functions
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*/
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/* With pc-relative modes the offset is calulated from the address of the
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* extension word. This address is not known until the instruction opcode(s)
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* have been emitted. Since this address is unknown, the offset from pc
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* cannot be calculated correctly, so it cannot immediately be decided whether
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* to use mode 072 (pc-relative with 16 bit offset) or mode 073 (pc_relative
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* with possibly 32 bit offset) Because of this, instruction opcodes
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* are not really emitted right away, but temporarily stored. This way
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* the address of the extension word is known so the offset can be calculated
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* correctly and it then can be decided to use mode 072 or 073; this can be
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* altered in the instruction opcode, if necessary. For the sake of consistency
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* the effective address(es) are also stored temporarily. The instruction is
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* then emitted in one go, by emit_instr().
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*/
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void emit_instr(void)
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{
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register instr_t *ip;
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for (ip=instr; ip<instrp; emit2((ip++)->i_word)) {
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#ifdef RELOCATION
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RELOMOVE(relonami, ip->i_relonami);
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if (ip->i_reloinfo)
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newrelo(ip->i_relotype, ip->i_reloinfo | RELBR | RELWR);
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#endif
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}
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}
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#ifdef RELOCATION
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void t_emit2(short word, short relotype, int reloinfo, valu_t relnm)
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#else
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void t_emit2(short word)
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#endif
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{
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#ifdef RELOCATION
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if ((instrp->i_reloinfo = reloinfo)) {
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RELOMOVE(instrp->i_relonami, relnm);
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instrp->i_relotype = relotype;
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}
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#endif
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instrp->i_word = word;
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instrp++;
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dot_offset += 2;
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}
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#ifdef RELOCATION
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void t_emit4(long words, short relotype, int reloinfo, valu_t relnm)
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#else
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void t_emit4(long words)
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#endif
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{
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T_EMIT2((short)(words>>16), relotype, reloinfo, relnm);
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T_EMIT2((short)(words), 0, 0, 0);
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}
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void ea_1(int sz, int bits)
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{
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/* Because displacements come in three sizes (null displacement,
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* word and long displacement), each displacement requires
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* two bits in the bittable, so two calls to small. Sometimes
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* one of these calls is a dummy call.
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*/
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register int flag;
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register int sm, sm1, sm2;
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if (mrg_1 > 074)
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serror("no specials");
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if ((flag = eamode[mrg_1>>3]) == 0)
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if ((flag = eamode[010 + (mrg_1&07)]) == 0)
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flag = eamode[015 + (sz>>6)];
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if ((mrg_1 & 070) == 010)
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checksize(sz, 2|4);
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bits &= ~flag;
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if (bits)
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serror("bad addressing category");
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if (mrg_1==073 && (ffew_1 & 0200) == 0 && (bd_1.typ & ~S_DOT) == DOTTYP)
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bd_1.val -= (DOTVAL + dot_offset);
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if ( (mrg_1==073) || (mrg_1&070)==060 ) {
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sm = (
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(mrg_1==073 && (bd_1.typ & ~S_DOT)==DOTTYP)
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||
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(bd_1.typ == S_ABS)
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);
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if (small(sm && fitw(bd_1.val), 2)) {
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sm = (
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(sm1 = ((ffew_1 & 0307)==0 && fitb(bd_1.val)))
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||
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(sm2 = ((ffew_1 & 0307)==0100 && mrg_1==073))
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||
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(bd_1.val==0)
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);
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if (small(sm,2)) {
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if (sm1) { /* brief format extension */
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T_EMIT2((ffew_1&0177000) | lowb(bd_1.val),
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0, 0, 0);
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return;
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}
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if (sm2) {
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/* change mode to 072 in opcode word */
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instr->i_word &= ~1;
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T_EMIT2(loww(bd_1.val), 0, 0, 0);
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return;
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}
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ffew_1 &= ~040; /* null displacement */
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}
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else
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ffew_1 &= ~020; /* word displacement */
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} else
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sm = small(0,2); /* dummy call */
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if (ffew_1 & 3) {
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sm = (od_1.typ == S_ABS);
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if (small(sm && fitw(od_1.val), 2))
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ffew_1 &= small(od_1.val==0, 2) ? ~2 : ~1;
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else
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sm = small(0,2); /* dummy call */
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}
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assert((ffew_1 & 0410) == 0400);
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T_EMIT2(ffew_1, 0, 0, 0);
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assert(ffew_1 & 060);
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switch(ffew_1 & 060) {
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case 020:
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break;
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case 040:
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T_EMIT2(loww(bd_1.val), 0, 0, 0);
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break;
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case 060:
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T_EMIT4( bd_1.val,
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bd_1.typ,
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(mrg_1 == 073 && (ffew_1 & 0200) == 0)
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? RELPC|RELO4
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: RELO4,
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bd_rel1
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);
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}
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if (ffew_1 & 3) {
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switch(ffew_1 & 3) {
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case 1:
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break;
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case 2:
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T_EMIT2(loww(od_1.val), 0, 0, 0);
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break;
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case 3:
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T_EMIT4(od_1.val, od_1.typ, RELO4, od_rel1);
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}
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}
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return; /* mode 060 and 073 have been dealt with */
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}
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if (flag & FITW)
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if (
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! fitw(bd_1.val)
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&&
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(mrg_1 != 074 || ! fit16(bd_1.val))
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)
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nofit();
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if (flag & FITB) {
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if (
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! fitb(bd_1.val)
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&&
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(mrg_1 != 074 || ! fit8(bd_1.val))
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)
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nofit();
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if (mrg_1 == 074)
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bd_1.val &= 0xFF;
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}
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if (flag & PUTL)
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T_EMIT4(bd_1.val, bd_1.typ, (flag>>8), bd_rel1);
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if (flag & PUTW)
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T_EMIT2(loww(bd_1.val), bd_1.typ, (flag>>8), bd_rel1);
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}
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void ea_2(int sz, int bits)
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{
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mrg_1 = mrg_2;
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bd_1 = bd_2;
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od_1 = od_2;
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ffew_1 = ffew_2;
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RELOMOVE(bd_rel1, bd_rel2);
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RELOMOVE(od_rel1, od_rel2);
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ea_1(sz, bits);
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}
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void checksize(int sz, int bits)
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{
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if ((bits & (1 << (sz>>6))) == 0)
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serror("bad size");
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}
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void check_fsize(int sz, int size)
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{
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if (sz != size)
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serror("bad size");
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}
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void ch_sz_dreg(int size, int mode)
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{
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if (mode == 0 &&
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(size == FSIZE_X || size == FSIZE_P || size == FSIZE_D))
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serror("illegal size for data register");
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}
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int checkscale(valu_t val)
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{
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int v = val;
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if (v != val) v = 0;
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switch(v) {
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case 1: return 0;
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case 2: return 1<<9;
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case 4: return 2<<9;
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case 8: return 3<<9;
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default: serror("bad scale"); return 0;
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}
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}
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void badoperand(void)
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{
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serror("bad operand(s)");
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}
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void shift_op(int opc, int sz)
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{
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if (mrg_1 < 010 && mrg_2 < 010) {
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T_EMIT2((opc & 0170470) | sz | mrg_1<<9 | mrg_2, 0, 0, 0);
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return;
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}
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if (bd_1.typ != S_ABS || mrg_1 != 074) {
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badoperand();
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return;
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}
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if (mrg_2 < 010) {
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fit(fit3(bd_1.val));
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T_EMIT2((opc & 0170430) | sz | low3(bd_1.val)<<9 | mrg_2,0,0,0);
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return;
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}
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checksize(sz, 2);
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fit(bd_1.val == 1);
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T_EMIT2((opc & 0177700) | mrg_2, 0, 0, 0);
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ea_2(SIZE_W, MEM|ALT);
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}
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void bitop(int opc)
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{
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register int bits;
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bits = DTA|ALT;
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if (opc == 0 && (mrg_1 < 010 || mrg_2 != 074))
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bits = DTA;
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if (mrg_1 < 010) {
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T_EMIT2(opc | 0400 | mrg_1<<9 | mrg_2, 0, 0, 0);
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ea_2(0, bits);
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return;
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}
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if (mrg_1 == 074) {
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T_EMIT2(opc | 04000 | mrg_2, 0, 0, 0);
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ea_1(SIZE_W, 0);
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ea_2(0, bits);
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return;
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}
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badoperand();
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}
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void bitfield(int opc, int extension)
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{
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T_EMIT2(opc | mrg_2, 0, 0, 0);
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T_EMIT2(extension, 0, 0, 0);
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ea_2(SIZE_L, (mrg_2 < 010) ? 0 : (CTR | ALT));
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}
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void add(int opc, int sz)
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{
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if ((mrg_2 & 070) == 010)
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checksize(sz, 2|4);
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if (
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mrg_1 == 074
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&&
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small(
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bd_1.typ==S_ABS && fit3(bd_1.val),
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sz==SIZE_L ? 4 : 2
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)
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) {
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T_EMIT2((opc&0400) | 050000 | low3(bd_1.val)<<9 | sz | mrg_2,
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0, 0, 0);
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ea_2(sz, ALT);
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return;
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}
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if (mrg_1 == 074 && (mrg_2 & 070) != 010) {
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T_EMIT2((opc&03000) | sz | mrg_2, 0, 0, 0);
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ea_1(sz, 0);
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ea_2(sz, DTA|ALT);
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return;
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}
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if ((mrg_2 & 070) == 010) {
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T_EMIT2((opc&0170300) | (mrg_2&7)<<9 | sz<<1 | mrg_1, 0, 0, 0);
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ea_1(sz, 0);
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return;
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}
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if (to_dreg(opc, sz, 0))
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return;
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if (from_dreg(opc, sz, ALT|MEM))
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return;
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badoperand();
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}
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void and(int opc, int sz)
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{
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if (mrg_1 == 074 && mrg_2 >= 076) { /* ccr or sr */
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if (sz != SIZE_NON)
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checksize(sz, mrg_2==076 ? 1 : 2);
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else
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sz = (mrg_2==076 ? SIZE_B : SIZE_W);
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T_EMIT2((opc&07400) | sz | 074, 0, 0, 0);
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ea_1(sz, 0);
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return;
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}
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if (sz == SIZE_NON)
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sz = SIZE_DEF;
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if (mrg_1 == 074) {
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T_EMIT2((opc&07400) | sz | mrg_2, 0, 0, 0);
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ea_1(sz, 0);
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ea_2(sz, DTA|ALT);
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return;
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}
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if ((opc & 010000) == 0 && to_dreg(opc, sz, DTA))
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return;
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if (from_dreg(opc, sz, (opc & 010000) ? DTA|ALT : ALT|MEM))
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return;
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badoperand();
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}
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int to_dreg(int opc, int sz, int bits)
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{
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if ((mrg_2 & 070) != 000)
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return(0);
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T_EMIT2((opc & 0170000) | sz | (mrg_2&7)<<9 | mrg_1, 0, 0, 0);
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ea_1(sz, bits);
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return(1);
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}
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int from_dreg(int opc, int sz, int bits)
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{
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if ((mrg_1 & 070) != 000)
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return(0);
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T_EMIT2((opc & 0170000) | sz | (mrg_1&7)<<9 | 0400 | mrg_2, 0, 0, 0);
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ea_2(sz, bits);
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return(1);
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}
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void cmp(int sz)
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{
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register int opc;
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if ((mrg_1&070) == 030 && (mrg_2&070) == 030) {
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T_EMIT2(0130410 | sz | (mrg_1&7) | (mrg_2&7)<<9, 0, 0, 0);
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return;
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}
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if (mrg_1 == 074 && (mrg_2 & 070) != 010) {
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if (mrg_2==074)
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badoperand();
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T_EMIT2(06000 | sz | mrg_2, 0, 0, 0);
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ea_1(sz, 0);
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ea_2(sz, DTA);
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return;
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}
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if (mrg_2 < 020) {
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if (mrg_2 >= 010) {
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checksize(sz, 2|4);
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opc = 0130300 | sz<<1;
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mrg_2 &= 7;
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} else
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opc = 0130000 | sz;
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T_EMIT2(opc | mrg_2<<9 | mrg_1, 0, 0, 0);
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ea_1(sz, 0);
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return;
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}
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badoperand();
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}
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void link_instr(int sz, int areg)
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{
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if (sz == SIZE_NON) {
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if (bd_2.typ == S_ABS && fitw(bd_2.val))
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sz = SIZE_W;
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else
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sz = SIZE_L;
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}
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checksize(sz, 2|4);
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if (sz == SIZE_W)
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T_EMIT2(047120 | areg, 0, 0, 0);
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else /* sz == SIZE_L */
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T_EMIT2(044010 | areg, 0, 0, 0);
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ea_2(sz, 0);
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}
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void move(int sz)
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{
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register int opc;
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if (mrg_1 > 074 || mrg_2 > 074) {
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move_special(sz);
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return;
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}
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if (sz == SIZE_NON)
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sz = SIZE_DEF;
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if (
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mrg_2<010
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&&
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mrg_1==074
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&&
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sz==SIZE_L
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&&
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small(bd_1.typ==S_ABS && fitb(bd_1.val), 4)
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) {
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T_EMIT2(070000 | mrg_2<<9 | lowb(bd_1.val), 0, 0, 0);
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return;
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}
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switch (sz) {
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case SIZE_B: opc = 010000; break;
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case SIZE_W: opc = 030000; break;
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case SIZE_L: opc = 020000; break;
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}
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T_EMIT2(opc | mrg_1 | (mrg_2&7)<<9 | (mrg_2&070)<<3, 0, 0, 0);
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ea_1(sz, 0);
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ea_2(sz, ALT);
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}
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void move_special(int sz)
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{
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if (mrg_2 >= 076) {
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if (sz != SIZE_NON)
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checksize(sz, 2);
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T_EMIT2(042300 | (mrg_2==076?0:01000) | mrg_1, 0, 0, 0);
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ea_1(SIZE_W, DTA);
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return;
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}
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if (mrg_1 >= 076) {
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if (sz != SIZE_NON)
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checksize(sz, 2);
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T_EMIT2(040300 | (mrg_1==076?01000:0) | mrg_2, 0, 0, 0);
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ea_2(SIZE_W, DTA|ALT);
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return;
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}
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if (sz != SIZE_NON)
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checksize(sz, 4);
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if (mrg_1==075 && (mrg_2&070)==010) {
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T_EMIT2(047150 | (mrg_2&7), 0, 0, 0);
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return;
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}
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if (mrg_2==075 && (mrg_1&070)==010) {
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T_EMIT2(047140 | (mrg_1&7), 0, 0, 0);
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return;
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}
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badoperand();
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}
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void movem(int dr, int sz, int regs)
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{
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register int i;
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if ((mrg_2>>3) == 04) {
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regs = reverse(regs, 16);
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}
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checksize(sz, 2|4);
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if ((mrg_2>>3)-3 == dr)
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badoperand();
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T_EMIT2(044200 | dr<<10 | (sz & 0200) >> 1 | mrg_2, 0, 0, 0);
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T_EMIT2(regs, 0, 0, 0);
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i = CTR;
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if (dr == 0 && (mrg_2&070) == 040)
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i = MEM;
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if (dr != 0 && (mrg_2&070) == 030)
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i = MEM;
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if (dr == 0)
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i |= ALT;
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ea_2(sz, i);
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}
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int reverse(register int regs, int max)
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{
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register int r, i;
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r = regs; regs = 0;
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for (i = max; i > 0; i--) {
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regs <<= 1;
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if (r & 1)
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regs++;
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r >>= 1;
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}
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return regs;
|
|
}
|
|
|
|
void movep(int sz)
|
|
{
|
|
checksize(sz, 2|4);
|
|
if (mrg_1<010 && (mrg_2&070)==050) {
|
|
T_EMIT2(0610 | (sz & 0200)>>1 | mrg_1<<9 | (mrg_2&7), 0, 0, 0);
|
|
ea_2(sz, 0);
|
|
return;
|
|
}
|
|
if (mrg_2<010 && (mrg_1&070)==050) {
|
|
T_EMIT2(0410 | (sz & 0200)>>1 | mrg_2<<9 | (mrg_1&7), 0, 0, 0);
|
|
ea_1(sz, 0);
|
|
return;
|
|
}
|
|
badoperand();
|
|
}
|
|
|
|
void branch(int opc, expr_t exp)
|
|
{
|
|
register int sm;
|
|
|
|
exp.val -= (DOTVAL + 2);
|
|
if ((pass == PASS_2)
|
|
&&
|
|
(exp.val > 0)
|
|
&&
|
|
((exp.typ & S_DOT) == 0)
|
|
)
|
|
exp.val -= DOTGAIN;
|
|
sm = fitw(exp.val);
|
|
if ((exp.typ & ~S_DOT) != DOTTYP)
|
|
sm = 0;
|
|
if (small(sm,2)) {
|
|
if (small(fitb(exp.val),2)) {
|
|
if (exp.val == 0)
|
|
T_EMIT2(047161, 0, 0, 0); /* NOP */
|
|
else if (exp.val == -1) {
|
|
T_EMIT2(047161, 0, 0, 0);
|
|
serror("bad branch offset");
|
|
} else
|
|
T_EMIT2(opc | lowb(exp.val), 0, 0, 0);
|
|
} else {
|
|
T_EMIT2(opc, 0, 0, 0);
|
|
T_EMIT2(loww(exp.val), 0, 0, 0);
|
|
}
|
|
return;
|
|
}
|
|
sm = small(0,2); /* dummy call; two calls to small per branch */
|
|
T_EMIT2(opc | 0377, 0, 0, 0); /* 4 byte offset */
|
|
T_EMIT4(exp.val, exp.typ, RELPC|RELO4, relonami);
|
|
}
|
|
|
|
void cpbcc(int opc, expr_t exp)
|
|
{
|
|
register int sm;
|
|
|
|
exp.val -= (DOTVAL + 2);
|
|
if ((pass == PASS_2)
|
|
&&
|
|
(exp.val > 0)
|
|
&&
|
|
((exp.typ & S_DOT) == 0)
|
|
)
|
|
exp.val -= DOTGAIN;
|
|
sm = fitw(exp.val);
|
|
if ((exp.typ & ~S_DOT) != DOTTYP)
|
|
sm = 0;
|
|
if (small(sm,2)) {
|
|
T_EMIT2(opc, 0, 0, 0);
|
|
T_EMIT2(loww(exp.val), 0, 0, 0);
|
|
return;
|
|
}
|
|
|
|
T_EMIT2(opc | 0100, 0, 0, 0); /* 4 byte offset */
|
|
/* NB: no coprocessor defined extension words are emitted */
|
|
T_EMIT4(exp.val, exp.typ, RELPC|RELO4, relonami);
|
|
}
|
|
|
|
void ea7071(int sz)
|
|
{
|
|
mrg_2 = 071;
|
|
switch (sz) {
|
|
case SIZE_B:
|
|
badoperand();
|
|
case SIZE_W:
|
|
mrg_2 = 070;
|
|
case SIZE_L:
|
|
return;
|
|
case SIZE_NON:
|
|
break;
|
|
}
|
|
/* If this absolute address is in program space, and if we
|
|
* can assume that the only references to program space are made
|
|
* by instructins like 'jsr', 'jmp', 'lea' and 'pea', it might
|
|
* be possible to use a (PC,d16) effective address mode instead
|
|
* of absolute long. This is done here. If this scheme is in
|
|
* some way undesirable (e.g. when references to program space
|
|
* are made by instructions with more than one opcode word or by
|
|
* second effective addresses in instructions), the rest
|
|
* of this routine can simply be removed and replaced by the
|
|
* next two lines (which of course are in comment brackets now).
|
|
if (small(bd_2.typ == S_ABS && fitw(bd_2.val), 2))
|
|
mrg_2 = 070;
|
|
*/
|
|
if (pass == PASS_1) {
|
|
/* Reserve a bit in the bittable; in the following
|
|
* passes one call to small() will be done, but know yet
|
|
* which one, because bd_2.typ cannot be trusted yet.
|
|
*/
|
|
small(0, 2);
|
|
return;
|
|
}
|
|
if ((bd_2.typ & ~S_DOT) == DOTTYP) {
|
|
/* the "off" variable fixes the problem described above,
|
|
* e.g., when references to program space are made by
|
|
* instructions with more than one opcode word.
|
|
*/
|
|
int off = 2;
|
|
|
|
switch(curr_instr) {
|
|
case MOVEM:
|
|
case FMOVE:
|
|
case FMOVEM:
|
|
case FDYADIC:
|
|
case FMONADIC:
|
|
case FSINCOS:
|
|
case FSCC:
|
|
case FTST:
|
|
case DIVL:
|
|
case OP_RANGE:
|
|
case CALLM:
|
|
case CAS:
|
|
case CPSCC:
|
|
case CPTRAPCC:
|
|
case PFLUSH:
|
|
case PTEST:
|
|
case PMOVE:
|
|
case PLOAD:
|
|
off = 4;
|
|
break;
|
|
case MOVESP:
|
|
if (curr_size != 0) off = 4;
|
|
break;
|
|
case DIVMUL:
|
|
if (curr_size != SIZE_W) off = 4;
|
|
break;
|
|
}
|
|
if (small(fitw(bd_2.val-(DOTVAL+off)), 2)) {
|
|
bd_2.val -= (DOTVAL+off);
|
|
mrg_2 = 072;
|
|
}
|
|
} else
|
|
if (small(bd_2.typ == S_ABS && fitw(bd_2.val), 2))
|
|
mrg_2 = 070;
|
|
}
|
|
|
|
void fbranch(int opc, expr_t exp)
|
|
{
|
|
register int sm;
|
|
|
|
exp.val -= (DOTVAL + 2);
|
|
if ((pass == PASS_2)
|
|
&&
|
|
(exp.val > 0)
|
|
&&
|
|
((exp.typ & S_DOT) == 0)
|
|
)
|
|
exp.val -= DOTGAIN;
|
|
sm = fitw(exp.val);
|
|
if ((exp.typ & ~S_DOT) != DOTTYP)
|
|
sm = 0;
|
|
if (small(sm,2)) {
|
|
T_EMIT2(0170200|co_id|opc, 0, 0, 0);
|
|
T_EMIT2(loww(exp.val), 0, 0, 0);
|
|
return;
|
|
}
|
|
T_EMIT2(0170300|co_id|opc, 0, 0, 0); /* 4 byte offset */
|
|
T_EMIT4(exp.val, exp.typ, RELPC|RELO4, relonami);
|
|
}
|