416 lines
10 KiB
C
416 lines
10 KiB
C
#define RCSID4 "$Header$"
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/*
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* (c) copyright 1983 by the Vrije Universiteit, Amsterdam, The Netherlands.
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*
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* This product is part of the Amsterdam Compiler Kit.
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*
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* Permission to use, sell, duplicate or disclose this software must be
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* obtained in writing. Requests for such permissions may be sent to
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*
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* Dr. Andrew S. Tanenbaum
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* Wiskundig Seminarium
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* Vrije Universiteit
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* Postbox 7161
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* 1007 MC Amsterdam
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* The Netherlands
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*
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*/
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/* Author: Ed Keizer */
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operation:
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BR expr
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/* format 0 */
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{ dot_adjust(&$2) ; form0($1) ; disp(&$2, RELPC) ;}
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| WAIT
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/* format 1 */
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{ form1($1) ;}
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| BSR expr
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/* format 1 */
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{ dot_adjust(&$2) ; form1($1) ; disp(&$2, RELPC) ;}
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| RET expr
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/* format 1 */
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{ form1($1) ; disp(&$2, 0) ;}
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| SAVE reg_list
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/* format 1 */
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{ form1($1) ; emit1(reg_list($2,id_op($1)!=0x6)) ;}
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| ENTER reg_list ',' expr
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/* format 1 */
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{ form1($1) ; emit1(reg_list($2,0)) ; disp(&$4, 0) ;}
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| LPR AREG ',' gen1
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/* format 2 */
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{ if ( id_op($1)==0x2 ) not_imm(&mode1) ;
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form2($1,$2) ; gen1($1) ;
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}
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| SEQ gen1
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/* format 2 */
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{ form2($1,id_cc($1)) ; gen1($1) ; not_imm(&mode1) ;}
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| MOVQ absexp ',' gen1
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/* format 2 */
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{
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if ( !fit4($2) ) {
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serror("Constant too large") ;
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}
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form2($1,low4($2)) ; gen1($1) ;
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if ( id_op($1)!=0x1 ) not_imm(&mode1) ; /* !cmp */
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}
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| ACB absexp ',' gen1 ',' expr
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/* format 2 */
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{
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dot_adjust(&$6) ;
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if (!fit4($2) ) {
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serror("Constant too large") ;
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}
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form2($1,low4($2)) ; gen1($1) ; not_imm(&mode1) ;
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disp(&$6, RELPC) ;
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}
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| ADJSP gen1
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/* format 3 */
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{
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if ( id_op($1)==0 ) not_imm(&mode1) ; /* cxpd */
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form3($1) ; gen1($1) ;}
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| JSR gen1
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/* format 3 */
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{
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#ifndef NO_OPTIM
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if ( mode1.m_mode==0x15 ) { /* Absolute */
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dot_adjust(&mode1.m_expr1) ;
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RELOMOVE(relonami, mode1.m_rel1);
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form1(0) ; disp(&mode1.m_expr1, RELPC) ; /* bsr */
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} else
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#endif
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{ form3($1) ; gen1($1) ; }
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not_imm(&mode1) ;
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}
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| JUMP gen1
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/* format 3 */
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{
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#ifndef NO_OPTIM
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if ( mode1.m_mode==0x15 ) { /* Absolute */
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dot_adjust(&mode1.m_expr1) ;
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RELOMOVE(relonami, mode1.m_rel1);
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form0(B_TRUE) ; disp(&mode1.m_expr1, RELPC) ; /* br */
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} else
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#endif
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{ form3($1) ; gen1($1) ; }
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not_imm(&mode1) ;
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}
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| ADD_I gen1 ',' gen2
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/* format 4 */
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{
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register opc ;
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opc=id_op($1) ;
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if ( opc==0x9 ) not_imm(&mode1) ; /* addr */
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if ( opc!=0x1 ) not_imm(&mode2) ; /* !cmp */
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#ifndef NO_OPTIM
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if ( mode1.m_mode==0x14 && /* Immediate */
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(mode1.m_expr1.typ & ~S_EXT) == S_ABS &&
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(
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(fit4(mode1.m_expr1.val) &&
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(opc==0 || opc==1 || opc==5))
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||
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(fit4(-mode1.m_expr1.val) &&
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(opc==8))
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)
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)
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{
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/* Warning, an absolute expression derived
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from a symbol that is defined after
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use might - if the value now suddenly fits -
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cause failed assertions in newlabel
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*/
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/* add, cmp, mov */
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/* added: the subtract of a signed
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* short is the same as the add
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* of the negation of that short
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* so: subi short,x == addqi -short,x
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* 19/04/85 h.m.kodden,m.j.a.leliveld
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*/
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if (opc==8) /* do the negate */
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mode1.m_expr1.val =
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(~mode1.m_expr1.val+1)&0xF;
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opc=low4(mode1.m_expr1.val) ;
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mode1= mode2 ;
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form2($1,opc) ; gen1($1) ;
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} else
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#endif
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{ form4($1) ; gengen($1) ; }
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}
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| SETCFG cpu_opts
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/* format 5 */
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{ form5($1,$2) ;}
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| MOVS string_opts
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/* format 5 */
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{ form5($1,($2)|id_cc($1)) ;}
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| COM gen1 ',' gen2
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/* format 6 */
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{ form6($1) ; gengen($1) ; not_imm(&mode2) ;}
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| MUL_I gen1 ',' gen2
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/* format 7 */
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{
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if ( id_op($1)==0x9 || id_op($1)==0xB ) {
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/* mei or dei */
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switch ( mode2.m_mode ) {
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case 1 : case 3 : case 5 : case 7 :
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serror("register must be even") ;
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}
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}
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form7($1) ; gengen($1) ; not_imm(&mode2) ;
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}
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| MOVID gen1 ',' gen2
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/* format 7 */
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{ form7x($1,id_g1($1)) ; gengen($1) ; not_imm(&mode2) ;}
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| MOVM gen1 ',' gen2 ',' expr
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/* format 7 */
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{
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register s_size ;
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s_size= id_g1($1)+1 ;
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/* $6.val= $6.val*s_size - s_size ; */
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$6.val= $6.val -1 ;
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form7($1) ; gengen($1) ; disp(&$6, 0) ;
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not_imm(&mode1) ; not_imm(&mode2) ;
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}
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| INSS gen1 ',' gen2 ',' absexp ',' absexp
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/* format 7 */
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{
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if ( ( $6<0 || $6>7 || $8<1 || $8>32 )
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) { serror("Constant out of bounds") ; }
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form7($1) ; gengen($1) ;
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if ( id_op($1)==0x3 ) not_imm(&mode1) ; /* exts */
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not_imm(&mode2) ;
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emit1((((int)$6)<<5)+(int)$8-1) ;
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}
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| FFS gen1 ',' gen2
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/* format 8 */
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{ form8($1,id_cc($1)) ; gengen($1) ; not_imm(&mode2) ;}
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| CHECK REG ',' gen1 ',' gen2
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/* format 8 */
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{
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form8($1,$2) ; gengen($1) ;
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if ( id_op($1)!=0x4 ) {
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not_imm(&mode1) ; /* check, cvtp */
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if ( id_op($1)==0x1 ) not_imm(&mode2) ;/*cvtp */
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}
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}
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| INS REG ',' gen1 ',' gen2 ',' expr
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/* format 8 */
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{
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form8($1,$2) ; gengen($1) ; disp(&$8, 0) ;
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if ( id_op($1)==0x0 ) not_imm(&mode1) ;
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not_imm(&mode2) ;
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}
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| MOVIF gen1 ',' fgen2
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/* format 9 */
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{
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assert( id_t1($1)==T_INT && id_t2($1)==T_FL ) ;
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form9($1,id_g1($1),id_g2($1)) ; gengen($1) ;
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not_imm(&mode2) ;
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}
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| MOVFL fgen1 ',' fgen2
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/* format 9 */
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{
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assert( id_t1($1)==T_FL && id_t2($1)==T_FL ) ;
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form9($1,id_g1($1),( id_g2($1)==F_LONG?3:2 )) ;
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gengen($1) ; not_imm(&mode2) ;
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}
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| TRUNC fgen1 ',' gen2
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/* format 9 */
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{
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assert( id_t1($1)==T_FL && id_t2($1)==T_INT ) ;
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form9($1,id_g2($1),id_g1($1)) ; gengen($1) ;
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not_imm(&mode2) ;
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}
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| LFSR gen1
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/* format 9 */
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{
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if ( id_op($1)==6 ) { /* SFSR */
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not_imm(&mode1) ;
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mode2.m_mode=mode1.m_mode ;
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mode1.m_mode=0 ;
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} else {
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mode2.m_mode=0 ;
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}
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form9($1,0,0) ;
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if ( id_op($1)==6 ) {
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mode1.m_mode=mode2.m_mode ;
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}
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gen1($1) ;
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}
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| ADD_F fgen1 ',' fgen2
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/* format 11 */
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{ if ( id_op($1)!=0x2 ) not_imm(&mode2) ; /* !CMPF */
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form11($1) ; gengen($1) ;
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}
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| RDVAL gen1
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/* format 14 */
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{ form14($1,0) ; gen1($1) ; not_imm(&mode1) ;}
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| LMR MREG ',' gen1
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/* format 14 */
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{
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form14($1,$2) ; gen1($1) ;
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if ( id_op($1)==0x3 ) not_imm(&mode1) ;
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}
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/* All remaining categories are not checked for
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illegal immediates */
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| LCR CREG ',' gen1
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/* format 15.0 */
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{ frm15_0($1,$2) ; gen1($1) ;}
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| CATST gen1
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/* format 15.0 */
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{ frm15_0($1,0) ; gen1($1) ;}
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| LCSR gen1
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/* format 15.1 */ /* Sure? */
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{ mode2.m_mode=0 ; frm15_1($1,0,0) ; gen1($1) ;}
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| CCVIS gen1 ',' gen2
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/* format 15.1 */
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{
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assert( id_t1($1)==T_INT && id_t2($1)==T_SLAVE ) ;
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frm15_1($1,id_g1($1),id_g2($1)) ; gengen($1) ;
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}
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| CCVSI gen1 ',' gen2
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/* format 15.1 */
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{
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assert( id_t1($1)==T_SLAVE && id_t2($1)==T_INT ) ;
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frm15_1($1,id_g2($1),id_g1($1)) ; gengen($1) ;
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}
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| CCVSS gen1 ',' gen2
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/* format 15.1 */
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{
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assert( id_t1($1)==T_SLAVE && id_t2($1)==T_SLAVE ) ;
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frm15_1($1,0,0) ; gengen($1) ; /* Sure? */
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}
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| CMOV gen1 ',' gen2
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/* format 15.5 */
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{ frm15_5($1) ; gengen($1) ;}
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;
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gen1 : { mode_ptr= &mode1 ; clrmode() ; } gen
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;
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gen2 : { mode_ptr= &mode2 ; clrmode() ; } gen
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;
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fgen1 : { mode_ptr= &mode1 ; clrmode() ; } fgen
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;
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fgen2 : { mode_ptr= &mode2 ; clrmode() ; } fgen
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;
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gen : gen_not_reg /* Every mode except register */
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| REG
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{ mode_ptr->m_mode= $1 ; }
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;
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fgen : gen_not_reg /* Every mode except register */
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| FREG
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{ mode_ptr->m_mode= $1 ; }
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;
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gen_not_reg: gen_a /* general mode with eff. address */
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| REG { mode_ptr->m_mode=$1 ;} index
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/* The register is supposed to contain the
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address
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*/
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| gen_a index /* As above, but indexed */
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| expr /* Immediate */
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{ mode_ptr->m_mode= 0x14 ;
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mode_ptr->m_expr1= $1 ;
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RELOMOVE(mode_ptr->m_rel1, relonami);
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}
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;
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gen_a : expr '(' REG ')' /* Register relative */
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{ mode_ptr->m_mode= 0x8 + $3 ;
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mode_ptr->m_ndisp= 1 ;
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mode_ptr->m_expr1= $1 ;
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RELOMOVE(mode_ptr->m_rel1, relonami);
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}
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| expr '(' AREG ')' /* Memory space */
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{ if ( $3<0x8 || $3>0xA ) badsyntax() ;
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mode_ptr->m_mode= 0x18 + ($3&3) ;
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mode_ptr->m_ndisp= 1 ;
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mode_ptr->m_expr1= $1 ;
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RELOMOVE(mode_ptr->m_rel1, relonami);
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}
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| expr '(' PC ')' /* Memory space */
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{ mode_ptr->m_mode= 0x1B ;
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mode_ptr->m_ndisp= 1 ;
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mode_ptr->m_expr1= $1 ;
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RELOMOVE(mode_ptr->m_rel1, relonami);
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dot_adjust(&mode_ptr->m_expr1) ;
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}
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| expr '('
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{ mode_ptr->m_expr2 = $1;
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RELOMOVE(mode_ptr->m_rel2, relonami);
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}
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expr '(' AREG ')' ')' /* Memory relative */
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{ if ( $6<0x8 || $6>0xA ) badsyntax() ;
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mode_ptr->m_mode= 0x10 + ($6&3) ;
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mode_ptr->m_ndisp= 2 ;
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mode_ptr->m_expr1= $4 ;
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RELOMOVE(mode_ptr->m_rel1, relonami);
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}
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| '@' expr /* Absolute */
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{ mode_ptr->m_mode= 0x15 ;
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mode_ptr->m_ndisp= 1 ;
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mode_ptr->m_expr1= $2 ;
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RELOMOVE(mode_ptr->m_rel1, relonami);
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}
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| EXTERNAL '(' expr ')'
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{ mode_ptr->m_mode= 0x16 ;
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mode_ptr->m_ndisp= 2 ;
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mode_ptr->m_expr1= $3 ;
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RELOMOVE(mode_ptr->m_rel1, relonami);
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}
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'+' expr /* External */
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{
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mode_ptr->m_expr2= $7 ;
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RELOMOVE(mode_ptr->m_rel2, relonami);
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}
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| TOS /* Top Of Stack */
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{ mode_ptr->m_mode= 0x17 ; }
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;
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index : '[' REG ':' INDICATOR ']' /* Indexed postfix */
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{ mode_ptr->m_index= (mode_ptr->m_mode<<3) | $2 ;
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mode_ptr->m_mode= ind_mode( $4 ) ;
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}
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;
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cpu_opts:
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'[' ']'
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{ $$=0 ;}
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| '[' cpu_list ']'
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{ $$= $2 ;}
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;
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cpu_list:
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INDICATOR
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{ $$=cpu_opt($1) ; }
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| cpu_list ',' INDICATOR
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{ $$= ($1) | cpu_opt($3) ;}
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;
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string_opts:
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{ $$=0 ;}
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| INDICATOR
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{ $$= string_opt($1) ; }
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| INDICATOR ',' INDICATOR
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{ if ( $1 != 'b' ||
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( $3 != 'u' && $3 != 'w' ) ) {
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serror("illegal string options") ;
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}
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$$ = string_opt($1)|string_opt($3) ;
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}
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;
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reg_list:
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'[' ']'
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{ $$=0 ;}
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| '[' reg_items ']'
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{ $$= $2 ;}
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;
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reg_items:
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REG
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{ $$= 1<<($1) ; }
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| reg_items ',' REG
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{ $$= ($1) | ( 1<<($3) ) ;}
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;
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