490 lines
12 KiB
C
490 lines
12 KiB
C
/* $Id: mach5.c, v3.3 25-Apr-89 AJM */
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void branch(word_t brtyp, word_t link, valu_t val)
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{
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valu_t offset;
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offset = val - DOTVAL - 8; /* Allow for pipeline */
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if ((offset & 0xFC000000) != 0 && (offset & 0xFC000000) != 0xFC000000){
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serror("offset out of range");
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}
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offset = offset>>2 & 0xFFFFFF;
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emit4(brtyp|link|offset);
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return;
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}
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void data(long opc, long ins, valu_t val, short typ)
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{
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valu_t tmpval;
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int adrflag = 0;
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if (typ == S_REG){ /* The argument is a register */
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emit4(opc|ins|val);
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return;
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}
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/* Do a bit of optimisation here, since the backend might produce instructions
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of the type MOV R0, R0, #0. We can ignore these. */
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if (((opc == ADD) || (opc == SUB)) && (val == 0)){ /* ADD or SUB 0 ? */
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if ((ins & 0x000F0000) == ((ins & 0x0000F000) << 4)) /* Same reg ? */
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return; /* Don't emit anything */
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}
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/* No optimisation, so carry on ... */
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ins |= 0x02000000; /* The argument is an immediate value */
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tmpval = val;
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if (opc == 0xff){ /* This is an ADR */
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adrflag = 1;
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opc = MOV;
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}
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if (typ == S_ABS){ /* An absolute value */
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if (calcimm(&opc, &tmpval, typ)){
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emit4(opc|ins|tmpval);
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return;
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}
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}
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tmpval = val;
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if (!adrflag){ /* Don't do this for ADRs */
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if (oursmall(calcimm(&opc, &tmpval, typ), 12)){
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emit4(opc|ins|tmpval);
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return;
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}
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}
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if (opc == MOV || opc == MVN || opc == ADD || opc == SUB){
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if (!bflag && pass == PASS_3){ /* Debugging info */
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/* warning("MOV/ADD extension"); */
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/* if (dflag)
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printf("value: %lx\n", val);*/
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}
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if (oursmall((val & 0xFFFF0000) == 0, 8)){
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putaddr(opc, ins, val, 2);
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return;
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}
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if (oursmall((val & 0xFF000000) == 0, 4)){
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putaddr(opc, ins, val, 3);
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return;
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}
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putaddr(opc, ins, val, 4);
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return;
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}
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if (pass == PASS_1)
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DOTVAL += 16; /* Worst case we can emit */
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else
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serror("immediate value out of range");
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return;
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}
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/* Calculate an immediate value. This is not as easy as it sounds, because
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the ARM uses an 8-bit value and 4-bit shift to encode the value into a
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12-bit field. Unfortunately this means that some numbers may not fit at
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all. */
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int calcimm(word_t *opc, valu_t *val,short typ)
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{
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int i = 0;
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if (typ == S_UND)
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return(0); /* Can't do anything with an undefined label */
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if ((*val & 0xFFFFFF00) == 0) /* Value is positive, but < 256, */
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return(1); /* so doesn't need a shift */
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if ((~*val & 0xFFFFFF00) == 0){ /* Value is negative, but < 256, */
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if (*opc == AND) /* so no shift required, only */
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{ /* inversion */
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*val = ~*val;
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*opc = BIC;
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return(1);
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}
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if (*opc == MOV)
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{
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*val = ~*val;
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*opc = MVN;
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return(1);
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}
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if (*opc == ADC)
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{
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*val = ~*val;
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*opc = SBC;
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return(1);
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}
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}
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if ((-1**val & 0xFFFFFF00) == 0){ /* Same idea ... */
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if (*opc == ADD)
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{
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*val *= -1;
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*opc = SUB;
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return(1);
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}
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if (*opc == CMP)
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{
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*val *= -1;
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*opc = CMN;
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return(1);
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}
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}
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do{ /* Now we need to shift */
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rotateleft2(&*val); /* Rotate left by two bits */
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i++;
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if((*val & 0xFFFFFF00) == 0){ /* Got a value < 256 */
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*val = *val|i<<8; /* OR in the shift */
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return(1);
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}
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if ((~*val & 0xFFFFFF00) == 0){ /* If negative, carry out */
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if (*opc == AND) /* inversion as before */
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{
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*val = ~*val|i<<8;
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*opc = BIC;
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return(1);
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}
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if (*opc == MOV)
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{
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*val = ~*val|i<<8;
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*opc = MVN;
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return(1);
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}
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if (*opc == ADC)
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{
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*val = ~*val|i<<8;
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*opc = SBC;
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return(1);
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}
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}
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}while(i<15);
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return(0); /* Failed if can't encode it after 16 rotates */
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}
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/* Calculate an offset in an address */
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word_t calcoffset(valu_t val)
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{
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if((val & 0xFFFFF000) == 0)
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return(val|0x00800000);
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val *= -1;
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if((val & 0xFFFFF000) == 0)
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return(val);
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serror("offset out of range");
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return(0);
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}
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/* This routine deals with STR and LDR instructions */
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void strldr(long opc, long ins, valu_t val)
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{
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long reg, reg2; /* The registers we are using */
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long tmpval;
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/* If the expression was a register, then just output it and save 24
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bytes */
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if (success){
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emit4(opc|ins|val);
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return;
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}
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reg = ins & 0x0000F000; /* Extract register from instruction */
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if (opc == LDR){
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tmpval = val - DOTVAL - 8;
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if (oursmall((tmpval & 0xFFFFF000) == 0, 16)){ /* If it's +ve */
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emit4(opc|ins|tmpval|0x018F0000); /* PC rel, up bit */
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return;
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}
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tmpval *= -1;
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if (oursmall((tmpval & 0xFFFFF000) == 0, 16)){ /* If it's -ve */
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emit4(opc|ins|tmpval|0x010F0000); /* PC rel, no up bit */
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return;
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}
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if (!bflag && pass == PASS_3){ /* Debugging info */
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/* warning("LDR address extension"); */
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if (dflag)
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printf("value: %lx\n", val);
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}
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opc = 0x03A00000; /* Set opc for putaddr */
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if (oursmall((val & 0xFFFF0000) == 0, 8)){
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putaddr(opc, ins & 0xFFBFFFFF, val, 2);
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emit4(0x05100000|ins|reg<<4);
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return;
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}
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if (oursmall((val & 0xFF000000) == 0, 4)){
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putaddr(opc, ins & 0xFFBFFFFF, val, 3);
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emit4(0x05100000|ins|reg<<4);
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return;
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}
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putaddr(opc, ins & 0xFFBFFFFF, val, 4);
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emit4(0x05100000|ins|reg<<4);
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return;
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}
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/* If the failure was an STR instruction, things are a bit more complicated as
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we can't overwrite the register before we store its value. We therefore
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need to use another register as well, which must be saved and restored.
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This register is saved on a stack pointed to by R12. Apart from this
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complication, the scheme is similar to the LDR above. */
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if (opc == STR){
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reg2 = reg >> 12; /* Use R6 as the second register, */
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reg2 = (reg2 == 6 ? 0 : 6); /* or R0 if we can't */
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tmpval = val - DOTVAL - 8;
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if (oursmall((tmpval & 0xFFFFF000) == 0, 24)){ /* If it's +ve */
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emit4(opc|ins|tmpval|0x018F0000); /* PC rel, up bit */
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return;
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}
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tmpval *= -1;
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if (oursmall((tmpval & 0xFFFFF000) == 0, 24)){ /* If it's -ve */
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emit4(opc|ins|tmpval|0x010F0000); /* PC rel, no up bit */
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return;
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}
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if (!bflag && pass == PASS_3){ /* Debugging info */
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/* warning("STR address extension"); */
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if (dflag)
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printf("value: %lx\n", val);
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}
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opc = 0x03A00000; /* Set opc for putaddr */
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if (oursmall((val & 0xFFFF0000) == 0, 8)){
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emit4(0xE92C0000|1<<reg2);
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putaddr(opc, (ins & 0xFFBF0FFF)|reg2<<12, val, 2);
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emit4(0x05000000|ins|reg2<<16);
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emit4(0xE8BC0000|1<<reg2);
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return;
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}
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if (oursmall((val & 0xFF000000) == 0, 4)){
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emit4(0xE92C0000|1<<reg2);
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putaddr(opc, (ins & 0xFFBF0FFF)|reg2<<12, val, 3);
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emit4(0x05000000|ins|reg2<<16);
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emit4(0xE8BC0000|1<<reg2);
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return;
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}
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emit4(0xE92C0000|1<<reg2);
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putaddr(opc, (ins & 0xFFBF0FFF)|reg2<<12, val, 4);
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emit4(0x05000000|ins|reg2<<16);
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emit4(0xE8BC0000|1<<reg2);
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return;
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}
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}
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/* This routine deals with ADR instructions. The ARM does not have a
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'calculate effective address' instruction, so we use ADD, SUB, MOV or
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MVN instead. ADR is not a genuine instruction, but is provided to make
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life easier. At present these are all calculated by using a MOV and
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successive ADDs. Even if the address will fit into a single MOV, we
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still use two instructions; the second is a no-op. This is to cure the
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optimisation problem with mobile addresses ! */
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void calcadr(word_t ins, word_t reg, valu_t val, short typ)
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{
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valu_t tmpval = val;
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word_t opc = 0xff; /* Dummy opc used as a flag for data() */
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/* First check that the address is in range */
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if (val < 0)
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tmpval = ~tmpval; /* Invert negative addresses for check */
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if ((tmpval & 0xFC000000) && (typ != S_UND)){
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serror("adr address out of range");
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return;
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}
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/* Can't do it PC relative, so use an absolute MOV instead */
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data (opc, ins|reg<<12, val, typ);
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return;
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}
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word_t calcshft(valu_t val, short typ, word_t styp)
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{
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if (typ == S_UND)
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return(0);
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if (val & 0xFFFFFFE0)
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serror("shiftcount out of range");
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if (styp && !val)
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warning("shiftcount 0");
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return((val & 0x1F)<<7);
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}
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void rotateleft2(long *x)
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{
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unsigned long bits;
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bits = *x & 0xC0000000;
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*x <<= 2 ;
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if (bits){
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bits >>= 30;
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*x |= bits;
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}
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return;
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}
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/*
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This routine overcomes the 12-bit encoding problem by outputting a number
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a byte at a time. For a MOV, it first uses a MOV, then successive ADDs.
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It will not use any more ADDs than needed to completely output the number.
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A similar approach is used for ADDs and SUBs.
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There is a problem here with optimisation in the third pass; if the
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instruction needed two ADDs in the second pass, but only one in the third
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pass, then the second ADD is replaced with a no-op. We cannot emit one
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less instruction, because that will upset other addresses.
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*/
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void putaddr(long opc, long ins, long val, int count)
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{
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long tmpval = val;
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long reg = ins & 0x0000F000;
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emit4(opc|ins|(val & 0x000000FF));
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tmpval = (val & 0x0000FF00) >> 8 | 0x00000C00;
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/* Decide what to use for the additional instructions */
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if (opc == 0x03a00000) /* This one is for strldr */
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opc = 0x02800000;
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if (opc == MOV)
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opc = ADD;
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if (opc == MVN)
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opc = SUB;
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if ((tmpval & 0x000000FF) != 0)
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emit4(opc|ins|reg<<4|tmpval);
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else
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emit4(0xF0000000); /* No-op if a zero argument */
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if (count == 3 || count == 4){ /* Must use three or more instructions */
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if ((val & 0xFFFF0000) != 0){
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tmpval = (val & 0x00FF0000) >> 16 | 0x00000800;
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emit4(opc|ins|reg<<4|tmpval);
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}
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else
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emit4(0xF0000000); /* No-op */
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}
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if (count == 4){ /* Must use four instructions */
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if ((val & 0xFF000000) != 0){
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tmpval = (val & 0xFF000000) >> 24 | 0x00000400;
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emit4(opc|ins|reg<<4|tmpval);
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}
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else
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emit4(0xF0000000); /* No-op */
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}
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return;
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}
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/* The following piece of code is stolen from comm7.c; it needs some minor
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fixes for the ARM, so it is included here rather than altering the existing
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code. It maintains a bit table to say whether or not an optimisation is
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possible. The original had some problems:
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(a). It assumed that the memory returned by malloc() was cleared to zero.
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This is true on a Sun, but not under Minix; small() should really
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use calloc() instead.
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(b). It assumed that if an optimisation was possible in pass 2, it must
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also be possible in pass 3, and produced an assertion error if it
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wasn't. This is OK for optimising things like long or short branch
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instructions on a 68000, but not for ADRs on the ARM. A previous
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optimisation may place an address out of 12-bit encoding range on
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pass 3, when it was in range on pass 2. However we have to be
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careful here .....
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*/
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#define PBITTABSZ 128
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static char *pbittab[PBITTABSZ];
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int oursmall(int fitsmall, int gain)
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{
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register int bit;
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register char *p;
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if (DOTSCT == NULL)
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nosect();
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if (bflag)
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return(0);
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if (nbits == BITCHUNK) {
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bitindex++;
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nbits = 0;
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if (bitindex == PBITTABSZ) {
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static int w_given;
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if (pass == PASS_1 && ! w_given) {
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w_given = 1;
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warning("bit table overflow");
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}
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return(0);
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}
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if (pbittab[bitindex] == 0 && pass == PASS_1) {
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if ((pbittab[bitindex] = malloc(MEMINCR)) == 0) {
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static int w2_given;
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if (!w2_given) {
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w2_given = 1;
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warning("out of space for bit table");
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}
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}
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}
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if (pbittab[bitindex] == 0)
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return (0);
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}
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bit = 1 << (nbits&7);
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p = pbittab[bitindex]+(nbits>>3);
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nbits++;
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switch (pass) {
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case PASS_1:
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*p = 0;
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return(0);
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case PASS_2:
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if (fitsmall) {
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DOTGAIN += gain;
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*p |= bit;
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}
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return(fitsmall);
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case PASS_3:
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if (!(fitsmall || (*p & bit) == 0)){
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printf("line: %ld - small failed\n", lineno);
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printf("fitsmall: %d bit: %d\n", fitsmall, (*p & bit));
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if (fitsmall)
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return(0);
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else
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serror("This one is fatal!");
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}
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return(*p & bit);
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default:
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assert(0);
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}
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/*NOTREACHED*/
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}
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