32ebc502c8
--HG-- branch : dtrg-videocore rename : mach/powerpc/as/.distr => mach/vc4/as/.distr rename : mach/powerpc/as/mach0.c => mach/vc4/as/mach0.c rename : mach/powerpc/as/mach1.c => mach/vc4/as/mach1.c rename : mach/powerpc/as/mach2.c => mach/vc4/as/mach2.c rename : mach/powerpc/as/mach3.c => mach/vc4/as/mach3.c rename : mach/powerpc/as/mach4.c => mach/vc4/as/mach4.c rename : mach/powerpc/as/mach5.c => mach/vc4/as/mach5.c rename : mach/i86/build.mk => mach/vc4/build.mk rename : mach/powerpc/libem/powerpc.h => mach/vc4/libem/videocore.h rename : mach/i86/libend/.distr => mach/vc4/libend/.distr rename : mach/i86/libend/edata.s => mach/vc4/libend/edata.s rename : mach/i86/libend/em_end.s => mach/vc4/libend/em_end.s rename : mach/i86/libend/end.s => mach/vc4/libend/end.s rename : mach/i86/libend/etext.s => mach/vc4/libend/etext.s rename : mach/powerpc/ncg/.distr => mach/vc4/ncg/.distr rename : mach/powerpc/ncg/mach.c => mach/vc4/ncg/mach.c rename : mach/powerpc/ncg/mach.h => mach/vc4/ncg/mach.h rename : mach/powerpc/ncg/table => mach/vc4/ncg/table rename : plat/pc86/descr => plat/rpi/descr
95 lines
4.6 KiB
C
95 lines
4.6 KiB
C
/*
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* VideoCore IV assembler for the ACK
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* © 2013 David Given
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* This file is redistributable under the terms of the 3-clause BSD license.
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* See the file 'Copying' in the root of the distribution for the full text.
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*/
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#include "binary.h"
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/* Integer registers */
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0, GPR, 0, "r0",
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0, GPR, 1, "r1",
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0, GPR, 2, "r2",
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0, GPR, 3, "r3",
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0, GPR, 4, "r4",
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0, GPR, 5, "r5",
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0, GPR, 6, "r6",
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0, GPR, 6, "fp",
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0, GPR, 7, "r7",
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0, GPR, 8, "r8",
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0, GPR, 9, "r9",
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0, GPR, 10, "r10",
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0, GPR, 11, "r11",
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0, GPR, 12, "r12",
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0, GPR, 13, "r13",
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0, GPR, 14, "r14",
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0, GPR, 15, "r15",
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0, GPR, 16, "r16",
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0, GPR, 17, "r17",
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0, GPR, 18, "r18",
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0, GPR, 19, "r19",
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0, GPR, 20, "r20",
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0, GPR, 21, "r21",
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0, GPR, 22, "r22",
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0, GPR, 23, "r23",
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0, GPR, 24, "r24",
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0, GPR, 25, "r25",
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0, GPR, 25, "sp",
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0, GPR, 26, "r26",
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0, GPR, 26, "lr",
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0, GPR, 27, "r27",
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0, GPR, 28, "r28",
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0, GPR, 29, "r29",
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0, GPR, 30, "r30",
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0, GPR, 30, "sr",
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0, GPR, 31, "r31",
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0, GPR, 31, "pc",
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/* Special instructions */
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0, OP, B16(00000000,00000001), "nop",
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0, OP, B16(00000000,00001010), "rti",
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0, OP_ONEREG, B16(00000000,01000000), "b",
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0, OP_ONEREG, B16(00000000,01100000), "bl",
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0, OP_ONELREG, B16(00000000,10000000), "tbb",
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0, OP_ONELREG, B16(00000000,10100000), "tbs",
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0, OP_ALU, B8(00000000), "mov",
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0, OP_ALU, B8(00000001), "cmn",
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0, OP_ALU, B8(00000010), "add",
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0, OP_ALU, B8(00000011), "bic",
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0, OP_ALU, B8(00000100), "mul",
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0, OP_ALU, B8(00000101), "eor",
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0, OP_ALU, B8(00000110), "sub",
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0, OP_ALU, B8(00000111), "and",
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0, OP_ALU, B8(00001000), "mvn",
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0, OP_ALU, B8(00001001), "ror",
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0, OP_ALU, B8(00001010), "cmp",
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0, OP_ALU, B8(00001011), "rsb",
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0, OP_ALU, B8(00001100), "btst",
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0, OP_ALU, B8(00001101), "or",
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0, OP_ALU, B8(00001110), "extu",
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0, OP_ALU, B8(00001111), "max",
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0, OP_ALU, B8(00010000), "bset",
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0, OP_ALU, B8(00010001), "min",
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0, OP_ALU, B8(00010010), "bclr",
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0, OP_ALU, B8(00010011), "adds2",
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0, OP_ALU, B8(00010100), "bchg",
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0, OP_ALU, B8(00010101), "adds4",
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0, OP_ALU, B8(00010110), "adds8",
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0, OP_ALU, B8(00010111), "adds16",
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0, OP_ALU, B8(00011000), "exts",
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0, OP_ALU, B8(00011001), "neg",
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0, OP_ALU, B8(00011010), "lsr",
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0, OP_ALU, B8(00011011), "clz",
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0, OP_ALU, B8(00011100), "lsl",
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0, OP_ALU, B8(00011101), "brev",
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0, OP_ALU, B8(00011110), "asr",
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0, OP_ALU, B8(00011111), "abs",
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