420 lines
12 KiB
C
420 lines
12 KiB
C
/*
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* (c) copyright 1987 by the Vrije Universiteit, Amsterdam, The Netherlands.
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* See the copyright notice in the ACK home directory, in the file "Copyright".
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*/
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#define RCSID3 "$Id$"
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/*
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* INTEL 80386 keywords
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*
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* No system registers for now ...
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*/
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0, USE16, 0, ".use16",
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0, USE32, 0, ".use32",
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0, R32, 0, "ax",
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0, R32, 1, "cx",
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0, R32, 2, "dx",
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0, R32, 3, "bx",
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0, R32, 4, "sp",
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0, R32, 5, "bp",
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0, R32, 6, "si",
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0, R32, 7, "di",
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0, R32, 0, "eax",
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0, R32, 1, "ecx",
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0, R32, 2, "edx",
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0, R32, 3, "ebx",
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0, R32, 4, "esp",
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0, R32, 5, "ebp",
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0, R32, 6, "esi",
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0, R32, 7, "edi",
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0, R8, 0, "al",
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0, R8, 1, "cl",
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0, R8, 2, "dl",
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0, R8, 3, "bl",
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0, R8, 4, "ah",
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0, R8, 5, "ch",
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0, R8, 6, "dh",
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0, R8, 7, "bh",
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0, RSEG, 0, "es",
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0, RSEG, 1, "cs",
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0, RSEG, 2, "ss",
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0, RSEG, 3, "ds",
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0, RSEG, 4, "fs",
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0, RSEG, 5, "gs",
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0, RSYSCR, 0, "cr0",
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0, RSYSCR, 2, "cr2",
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0, RSYSCR, 3, "cr3",
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0, RSYSDR, 0, "dr0",
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0, RSYSDR, 1, "dr1",
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0, RSYSDR, 2, "dr2",
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0, RSYSDR, 3, "dr3",
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0, RSYSDR, 6, "dr6",
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0, RSYSDR, 7, "dr7",
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0, RSYSTR, 3, "tr3", /* i486 */
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0, RSYSTR, 4, "tr4", /* i486 */
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0, RSYSTR, 5, "tr5", /* i486 */
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0, RSYSTR, 6, "tr6",
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0, RSYSTR, 7, "tr7",
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0, ADDOP, 000, "addb",
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0, ADDOP, 001, "add",
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0, ADDOP, 010, "orb",
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0, ADDOP, 011, "or",
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0, ADDOP, 020, "adcb",
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0, ADDOP, 021, "adc",
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0, ADDOP, 030, "sbbb",
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0, ADDOP, 031, "sbb",
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0, ADDOP, 040, "andb",
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0, ADDOP, 041, "and",
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0, ADDOP, 050, "subb",
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0, ADDOP, 051, "sub",
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0, ADDOP, 060, "xorb",
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0, ADDOP, 061, "xor",
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0, ADDOP, 070, "cmpb",
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0, ADDOP, 071, "cmp",
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0, BITTEST, 04, "bt",
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0, BITTEST, 05, "bts",
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0, BITTEST, 06, "btr",
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0, BITTEST, 07, "btc",
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0, CALFOP, 030+(0232<<8), "callf",
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0, CALFOP, 050+(0352<<8), "jmpf",
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0, CALLOP, 020+(0350<<8), "call",
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0, CALLOP, 040+(0351<<8), "jmp",
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0, ENTER, 0310, "enter",
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0, EXTEND, 0267, "movzx",
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0, EXTEND, 0266, "movzxb",
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0, EXTEND, 0277, "movsx",
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0, EXTEND, 0276, "movsxb",
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0, EXTOP, 0002, "lar",
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0, EXTOP, 0003, "lsl",
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0, EXTOP, 0274, "bsf",
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0, EXTOP, 0275, "bsr",
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0, EXTOP1, 0000, "sldt",
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0, EXTOP1, 0001, "sgdt",
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0, EXTOP1, 0010, "str",
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0, EXTOP1, 0011, "sidt",
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0, EXTOP1, 0020, "lldt",
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0, EXTOP1, 0021, "lgdt",
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0, EXTOP1, 0030, "ltr",
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0, EXTOP1, 0031, "lidt",
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0, EXTOP1, 0040, "verr",
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0, EXTOP1, 0041, "smsw",
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0, EXTOP1, 0050, "verw",
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0, EXTOP1, 0061, "lmsw",
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0, IMUL, 00, "imul",
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0, IMULB, 050, "imulb",
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0, INCOP, 000, "incb",
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0, INCOP, 001, "inc",
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0, INCOP, 010, "decb",
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0, INCOP, 011, "dec",
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0, INT, 0, "int",
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0, IOOP, 0344, "inb",
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0, IOOP, 0345, "in",
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0, IOOP, 0346, "outb",
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0, IOOP, 0347, "out",
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0, JOP, 0340, "loopne",
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0, JOP, 0340, "loopnz",
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0, JOP, 0341, "loope",
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0, JOP, 0341, "loopz",
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0, JOP, 0342, "loop",
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0, JOP, 0343, "jcxz",
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0, JOP, 0343, "jecxz",
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0, JOP2, 0000, "jo",
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0, JOP2, 0001, "jno",
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0, JOP2, 0002, "jb",
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0, JOP2, 0002, "jc",
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0, JOP2, 0002, "jnae",
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0, JOP2, 0003, "jae",
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0, JOP2, 0003, "jnb",
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0, JOP2, 0003, "jnc",
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0, JOP2, 0004, "je",
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0, JOP2, 0004, "jz",
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0, JOP2, 0005, "jne",
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0, JOP2, 0005, "jnz",
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0, JOP2, 0006, "jbe",
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0, JOP2, 0006, "jna",
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0, JOP2, 0007, "ja",
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0, JOP2, 0007, "jnbe",
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0, JOP2, 0010, "js",
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0, JOP2, 0011, "jns",
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0, JOP2, 0012, "jp",
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0, JOP2, 0012, "jpe",
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0, JOP2, 0013, "jnp",
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0, JOP2, 0013, "jpo",
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0, JOP2, 0014, "jl",
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0, JOP2, 0014, "jnge",
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0, JOP2, 0015, "jge",
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0, JOP2, 0015, "jnl",
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0, JOP2, 0016, "jle",
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0, JOP2, 0016, "jng",
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0, JOP2, 0017, "jg",
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0, JOP2, 0017, "jnle",
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0, LEAOP, 0142, "bound",
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0, LEAOP, 0215, "lea",
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0, LEAOP, 0304, "les",
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0, LEAOP, 0305, "lds",
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0, LEAOP2, 0262, "lss",
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0, LEAOP2, 0264, "lfs",
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0, LEAOP2, 0265, "lgs",
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0, LSHFT, 0244, "shld",
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0, LSHFT, 0254, "shrd",
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0, MOV, 0, "movb",
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0, MOV, 1, "mov",
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0, NOOP_1, 0140, "pusha",
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0, NOOP_1, 0140, "pushad",
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0, NOOP_1, 0141, "popa",
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0, NOOP_1, 0141, "popad",
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0, NOOP_1, 0156, "outsb",
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0, NOOP_1, 0157, "outs",
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0, NOOP_1, 0220, "nop",
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0, NOOP_1, 0230, "cbw",
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0, NOOP_1, 0230, "cwde", /* same opcode as cbw! */
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0, NOOP_1, 0231, "cdq", /* same opcode as cwd! */
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0, NOOP_1, 0231, "cwd",
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0, NOOP_1, 0233, "wait",
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0, NOOP_1, 0234, "pushf",
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0, NOOP_1, 0235, "popf",
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0, NOOP_1, 0236, "sahf",
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0, NOOP_1, 0237, "lahf",
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0, NOOP_1, 0244, "movsb",
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0, NOOP_1, 0245, "movs",
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0, NOOP_1, 0246, "cmpsb",
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0, NOOP_1, 0154, "insb",
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0, NOOP_1, 0247, "cmps",
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0, NOOP_1, 0155, "ins",
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0, NOOP_1, 0252, "stosb",
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0, NOOP_1, 0253, "stos",
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0, NOOP_1, 0254, "lodsb",
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0, NOOP_1, 0255, "lods",
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0, NOOP_1, 0256, "scasb",
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0, NOOP_1, 0257, "scas",
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0, NOOP_1, 0311, "leave",
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0, NOOP_1, 0316, "into",
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0, NOOP_1, 0317, "iret",
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0, NOOP_1, 0317, "iretd",
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0, NOOP_1, 0327, "xlat",
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0, NOOP_1, 0364, "hlt",
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0, NOOP_1, 0365, "cmc",
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0, NOOP_1, 0370, "clc",
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0, NOOP_1, 0371, "stc",
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0, NOOP_1, 0372, "cli",
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0, NOOP_1, 0373, "sti",
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0, NOOP_1, 0374, "cld",
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0, NOOP_1, 0375, "std",
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0, NOOP_1, 047, "daa",
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0, NOOP_1, 057, "das",
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0, NOOP_1, 067, "aaa",
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0, NOOP_1, 077, "aas",
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0, NOOP_2, 017+(06<<8), "clts",
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0, NOOP_2, 0324+(012<<8), "aam",
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0, NOOP_2, 0325+(012<<8), "aad",
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0, NOTOP, 020, "notb",
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0, NOTOP, 021, "not",
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0, NOTOP, 030, "negb",
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0, NOTOP, 031, "neg",
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0, NOTOP, 040, "mulb",
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0, NOTOP, 041, "mul",
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0, NOTOP, 060, "divb",
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0, NOTOP, 061, "div",
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0, NOTOP, 070, "idivb",
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0, NOTOP, 071, "idiv",
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0, PREFIX, 0144, "fseg",
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0, PREFIX, 0145, "gseg",
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0, OTOGGLE, 0146, "o16", /* operand size toggle */
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0, OTOGGLE, 0346, "o32", /* operand size toggle */
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0, ATOGGLE, 0147, "a16", /* address size toggle */
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0, ATOGGLE, 0347, "a32", /* address size toggle */
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0, PREFIX, 0360, "lock",
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0, PREFIX, 0362, "repne",
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0, PREFIX, 0362, "repnz",
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0, PREFIX, 0363, "rep",
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0, PREFIX, 0363, "repe",
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0, PREFIX, 0363, "repz",
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0, PREFIX, 046, "eseg",
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0, PREFIX, 056, "cseg",
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0, PREFIX, 066, "sseg",
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0, PREFIX, 076, "dseg",
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0, PUSHOP, 0, "push",
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0, PUSHOP, 1, "pop",
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0, RET, 0303, "ret",
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0, RET, 0313, "retf",
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0, ROLOP, 000, "rolb",
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0, ROLOP, 001, "rol",
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0, ROLOP, 010, "rorb",
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0, ROLOP, 011, "ror",
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0, ROLOP, 020, "rclb",
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0, ROLOP, 021, "rcl",
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0, ROLOP, 030, "rcrb",
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0, ROLOP, 031, "rcr",
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0, ROLOP, 040, "salb",
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0, ROLOP, 040, "shlb",
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0, ROLOP, 041, "sal",
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0, ROLOP, 041, "shl",
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0, ROLOP, 050, "shrb",
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0, ROLOP, 051, "shr",
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0, ROLOP, 070, "sarb",
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0, ROLOP, 071, "sar",
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0, SETCC, 0000, "seto",
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0, SETCC, 0001, "setno",
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0, SETCC, 0002, "setb",
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0, SETCC, 0002, "setnae",
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0, SETCC, 0003, "setae",
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0, SETCC, 0003, "setnb",
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0, SETCC, 0004, "sete",
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0, SETCC, 0004, "setz",
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0, SETCC, 0005, "setne",
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0, SETCC, 0005, "setnz",
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0, SETCC, 0006, "setbe",
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0, SETCC, 0006, "setna",
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0, SETCC, 0007, "seta",
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0, SETCC, 0007, "setnbe",
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0, SETCC, 0010, "sets",
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0, SETCC, 0011, "setns",
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0, SETCC, 0012, "setp",
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0, SETCC, 0012, "setpe",
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0, SETCC, 0013, "setnp",
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0, SETCC, 0013, "setpo",
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0, SETCC, 0014, "setl",
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0, SETCC, 0014, "setnge",
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0, SETCC, 0015, "setge",
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0, SETCC, 0015, "setnl",
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0, SETCC, 0016, "setle",
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0, SETCC, 0016, "setng",
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0, SETCC, 0017, "setg",
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0, SETCC, 0017, "setnle",
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0, TEST, 0, "testb",
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0, TEST, 1, "test",
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0, XCHG, 0, "xchgb",
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0, XCHG, 1, "xchg",
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0, ARPLOP, 0143, "arpl",
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/* Intel 80[23]87 coprocessor keywords */
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0, ST, 0, "st",
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0, FNOOP, FESC+1+(0xF0<<8), "f2xm1",
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0, FNOOP, FESC+1+(0xE1<<8), "fabs",
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0, FNOOP, FESC+1+(0xE0<<8), "fchs",
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0, FNOOP, FESC+3+(0xE2<<8), "fclex",
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0, FNOOP, FESC+6+(0xD9<<8), "fcompp",
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0, FNOOP, FESC+2+(0xE9<<8), "fucompp",
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0, FNOOP, FESC+1+(0xF6<<8), "fdecstp",
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0, FNOOP, FESC+3+(0xE1<<8), "fdisi",
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0, FNOOP, FESC+3+(0xE0<<8), "feni",
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0, FNOOP, FESC+1+(0xF7<<8), "fincstp",
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0, FNOOP, FESC+3+(0xE3<<8), "finit",
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0, FNOOP, FESC+1+(0xE8<<8), "fld1",
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0, FNOOP, FESC+1+(0xEA<<8), "fldl2e",
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0, FNOOP, FESC+1+(0xE9<<8), "fldl2t",
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0, FNOOP, FESC+1+(0xEC<<8), "fldlg2",
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0, FNOOP, FESC+1+(0xED<<8), "fldln2",
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0, FNOOP, FESC+1+(0xEB<<8), "fldpi",
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0, FNOOP, FESC+1+(0xEE<<8), "fldz",
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0, FNOOP, FESC+1+(0xD0<<8), "fnop",
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0, FNOOP, FESC+1+(0xF3<<8), "fpatan",
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0, FNOOP, FESC+1+(0xFF<<8), "fcos",
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0, FNOOP, FESC+1+(0xFE<<8), "fsin",
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0, FNOOP, FESC+1+(0xFB<<8), "fsincos",
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0, FNOOP, FESC+1+(0xF8<<8), "fprem",
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0, FNOOP, FESC+1+(0xF5<<8), "fprem1",
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0, FNOOP, FESC+1+(0xF2<<8), "fptan",
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0, FNOOP, FESC+1+(0xFC<<8), "frndint",
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0, FNOOP, FESC+1+(0xFD<<8), "fscale",
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0, FNOOP, FESC+1+(0xFA<<8), "fsqrt",
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0, FNOOP, FESC+1+(0xE4<<8), "ftst",
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0, FNOOP, FESC+1+(0xE5<<8), "fxam",
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0, FNOOP, FESC+1+(0xF4<<8), "fxtract",
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0, FNOOP, FESC+1+(0xF1<<8), "fyl2x",
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0, FNOOP, FESC+1+(0xF9<<8), "fyl2xp1",
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0, FMEM, FESC+6+(0<<11), "fiadds",
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0, FMEM, FESC+2+(0<<11), "fiaddl",
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0, FMEM, FESC+0+(0<<11), "fadds",
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0, FMEM, FESC+4+(0<<11), "faddd",
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0, FMEM, FESC+7+(4<<11), "fbld",
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0, FMEM, FESC+7+(6<<11), "fbstp",
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0, FMEM, FESC+6+(2<<11), "ficoms",
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0, FMEM, FESC+2+(2<<11), "ficoml",
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0, FMEM, FESC+0+(2<<11), "fcoms",
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0, FMEM, FESC+4+(2<<11), "fcomd",
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0, FMEM, FESC+6+(3<<11), "ficomps",
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0, FMEM, FESC+2+(3<<11), "ficompl",
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0, FMEM, FESC+0+(3<<11), "fcomps",
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0, FMEM, FESC+4+(3<<11), "fcompd",
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0, FMEM, FESC+6+(6<<11), "fidivs",
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0, FMEM, FESC+2+(6<<11), "fidivl",
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0, FMEM, FESC+0+(6<<11), "fdivs",
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0, FMEM, FESC+4+(6<<11), "fdivd",
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0, FMEM, FESC+6+(7<<11), "fidivrs",
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0, FMEM, FESC+2+(7<<11), "fidivrl",
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0, FMEM, FESC+0+(7<<11), "fdivrs",
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0, FMEM, FESC+4+(7<<11), "fdivrd",
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0, FMEM, FESC+7+(5<<11), "fildq",
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0, FMEM, FESC+7+(0<<11), "filds",
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0, FMEM, FESC+3+(0<<11), "fildl",
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0, FMEM, FESC+1+(0<<11), "flds",
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0, FMEM, FESC+5+(0<<11), "fldd",
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0, FMEM, FESC+3+(5<<11), "fldx",
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0, FMEM, FESC+1+(5<<11), "fldcw",
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0, FMEM, FESC+1+(4<<11), "fldenv",
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0, FMEM, FESC+6+(1<<11), "fimuls",
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0, FMEM, FESC+2+(1<<11), "fimull",
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0, FMEM, FESC+0+(1<<11), "fmuls",
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0, FMEM, FESC+4+(1<<11), "fmuld",
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0, FMEM, FESC+5+(4<<11), "frstor",
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0, FMEM, FESC+5+(6<<11), "fsave",
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0, FMEM, FESC+7+(2<<11), "fists",
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0, FMEM, FESC+3+(2<<11), "fistl",
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0, FMEM, FESC+1+(2<<11), "fsts",
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0, FMEM, FESC+5+(2<<11), "fstd",
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0, FMEM, FESC+7+(7<<11), "fistpq",
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0, FMEM, FESC+7+(3<<11), "fistps",
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0, FMEM, FESC+3+(3<<11), "fistpl",
|
|
0, FMEM, FESC+1+(3<<11), "fstps",
|
|
0, FMEM, FESC+5+(3<<11), "fstpd",
|
|
0, FMEM, FESC+3+(7<<11), "fstpx",
|
|
0, FMEM, FESC+1+(7<<11), "fstcw",
|
|
0, FMEM, FESC+1+(6<<11), "fstenv",
|
|
0, FMEM_AX, FESC+5+(7<<11), "fstsw",
|
|
0, FMEM, FESC+6+(4<<11), "fisubs",
|
|
0, FMEM, FESC+2+(4<<11), "fisubl",
|
|
0, FMEM, FESC+0+(4<<11), "fsubs",
|
|
0, FMEM, FESC+4+(4<<11), "fsubd",
|
|
0, FMEM, FESC+6+(5<<11), "fisubrs",
|
|
0, FMEM, FESC+2+(5<<11), "fisubrl",
|
|
0, FMEM, FESC+0+(5<<11), "fsubrs",
|
|
0, FMEM, FESC+4+(5<<11), "fsubrd",
|
|
|
|
0, FST_I, FESC+1+(0xC0<<8), "fld",
|
|
0, FST_I, FESC+5+(0xD0<<8), "fst",
|
|
0, FST_I, FESC+5+(0xD8<<8), "fstp",
|
|
0, FST_I, FESC+1+(0xC8<<8), "fxch",
|
|
0, FST_I, FESC+0+(0xD0<<8), "fcom",
|
|
0, FST_I, FESC+5+(0xE0<<8), "fucom",
|
|
0, FST_I, FESC+0+(0xD8<<8), "fcomp",
|
|
0, FST_I, FESC+5+(0xE8<<8), "fucomp",
|
|
0, FST_I, FESC+5+(0xC0<<8), "ffree",
|
|
|
|
0, FST_ST, FESC+0+(0xC0<<8), "fadd",
|
|
0, FST_ST, FESC+2+(0xC0<<8), "faddp",
|
|
0, FST_ST2, FESC+0+(0xF0<<8), "fdiv",
|
|
0, FST_ST2, FESC+2+(0xF0<<8), "fdivp",
|
|
0, FST_ST2, FESC+0+(0xF8<<8), "fdivr",
|
|
0, FST_ST2, FESC+2+(0xF8<<8), "fdivrp",
|
|
0, FST_ST, FESC+0+(0xC8<<8), "fmul",
|
|
0, FST_ST, FESC+2+(0xC8<<8), "fmulp",
|
|
0, FST_ST2, FESC+0+(0xE0<<8), "fsub",
|
|
0, FST_ST2, FESC+2+(0xE0<<8), "fsubp",
|
|
0, FST_ST2, FESC+0+(0xE8<<8), "fsubr",
|
|
0, FST_ST2, FESC+2+(0xE8<<8), "fsubrp",
|
|
|
|
/* Intel 486 instructions */
|
|
0, EXTOPBW, 0xC0, "xaddb",
|
|
0, EXTOPBW, 0xC1, "xadd",
|
|
0, EXTOPBW, 0xB0, "cmpxchgb",
|
|
0, EXTOPBW, 0xB1, "cmpxchg",
|
|
0, BSWAP, 0xC8, "bswap",
|
|
0, NOOP_2, 017+(010<<8), "invd",
|
|
0, EXTOP1, 071, "invlpg",
|
|
0, NOOP_2, 017+(011<<8), "wbinvd",
|
|
|