338 lines
9.8 KiB
C
338 lines
9.8 KiB
C
/*
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* (c) copyright 1987 by the Vrije Universiteit, Amsterdam, The Netherlands.
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* See the copyright notice in the ACK home directory, in the file "Copyright".
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*/
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#define RCSID3 "$Id$"
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/*
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* INTEL 8086 keywords
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*/
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{0, R16, 0, "ax"},
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{0, R16, 1, "cx"},
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{0, R16, 2, "dx"},
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{0, R16, 3, "bx"},
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{0, R16, 4, "sp"},
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{0, R16, 5, "bp"},
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{0, R16, 6, "si"},
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{0, R16, 7, "di"},
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{0, R8, 0, "al"},
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{0, R8, 1, "cl"},
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{0, R8, 2, "dl"},
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{0, R8, 3, "bl"},
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{0, R8, 4, "ah"},
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{0, R8, 5, "ch"},
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{0, R8, 6, "dh"},
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{0, R8, 7, "bh"},
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{0, RSEG, 0, "es"},
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{0, RSEG, 1, "cs"},
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{0, RSEG, 2, "ss"},
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{0, RSEG, 3, "ds"},
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{0, PREFIX, 046, "eseg"},
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{0, PREFIX, 056, "cseg"},
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{0, PREFIX, 066, "sseg"},
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{0, PREFIX, 076, "dseg"},
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{0, PREFIX, 0360, "lock"},
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{0, PREFIX, 0363, "rep"},
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{0, PREFIX, 0362, "repne"},
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{0, PREFIX, 0362, "repnz"},
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{0, PREFIX, 0363, "repe"},
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{0, PREFIX, 0363, "repz"},
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{0, NOOP_1, 047, "daa"},
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{0, NOOP_1, 057, "das"},
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{0, NOOP_1, 067, "aaa"},
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{0, NOOP_1, 077, "aas"},
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{0, NOOP_1, 0220, "nop"},
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{0, NOOP_1, 0230, "cbw"},
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{0, NOOP_1, 0231, "cwd"},
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{0, NOOP_1, 0233, "wait"},
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{0, NOOP_1, 0234, "pushf"},
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{0, NOOP_1, 0235, "popf"},
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{0, NOOP_1, 0236, "sahf"},
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{0, NOOP_1, 0237, "lahf"},
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{0, NOOP_1, 0244, "movsb"},
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{0, NOOP_1, 0245, "movs"},
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{0, NOOP_1, 0245, "movsw"},
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{0, NOOP_1, 0246, "cmpsb"},
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{0, NOOP_1, 0247, "cmps"},
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{0, NOOP_1, 0247, "cmpsw"},
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{0, NOOP_1, 0252, "stosb"},
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{0, NOOP_1, 0253, "stos"},
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{0, NOOP_1, 0253, "stosw"},
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{0, NOOP_1, 0254, "lodsb"},
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{0, NOOP_1, 0255, "lods"},
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{0, NOOP_1, 0255, "lodsw"},
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{0, NOOP_1, 0256, "scasb"},
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{0, NOOP_1, 0257, "scas"},
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{0, NOOP_1, 0257, "scasw"},
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{0, NOOP_1, 0316, "into"},
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{0, NOOP_1, 0317, "iret"},
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{0, NOOP_1, 0327, "xlat"},
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{0, NOOP_1, 0364, "hlt"},
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{0, NOOP_1, 0365, "cmc"},
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{0, NOOP_1, 0370, "clc"},
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{0, NOOP_1, 0371, "stc"},
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{0, NOOP_1, 0372, "cli"},
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{0, NOOP_1, 0373, "sti"},
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{0, NOOP_1, 0374, "cld"},
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{0, NOOP_1, 0375, "std"},
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{0, NOOP_2, 0324+012<<8, "aam"},
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{0, NOOP_2, 0325+012<<8, "aad"},
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{0, JOP, 0340, "loopne"},
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{0, JOP, 0340, "loopnz"},
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{0, JOP, 0341, "loope"},
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{0, JOP, 0341, "loopz"},
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{0, JOP, 0342, "loop"},
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{0, JOP, 0343, "jcxz"},
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{0, JOP, 0160, "jo"},
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{0, JOP, 0161, "jno"},
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{0, JOP, 0162, "jb"},
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{0, JOP, 0162, "jc"},
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{0, JOP, 0162, "jnae"},
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{0, JOP, 0163, "jae"},
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{0, JOP, 0163, "jnb"},
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{0, JOP, 0163, "jnc"},
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{0, JOP, 0164, "je"},
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{0, JOP, 0164, "jz"},
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{0, JOP, 0165, "jne"},
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{0, JOP, 0165, "jnz"},
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{0, JOP, 0166, "jbe"},
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{0, JOP, 0166, "jna"},
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{0, JOP, 0167, "ja"},
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{0, JOP, 0167, "jnbe"},
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{0, JOP, 0170, "js"},
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{0, JOP, 0171, "jns"},
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{0, JOP, 0172, "jp"},
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{0, JOP, 0172, "jpe"},
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{0, JOP, 0173, "jnp"},
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{0, JOP, 0173, "jpo"},
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{0, JOP, 0174, "jl"},
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{0, JOP, 0174, "jnge"},
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{0, JOP, 0175, "jge"},
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{0, JOP, 0175, "jnl"},
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{0, JOP, 0176, "jle"},
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{0, JOP, 0176, "jng"},
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{0, JOP, 0177, "jg"},
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{0, JOP, 0177, "jnle"},
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{0, PUSHOP, 0, "push"},
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{0, PUSHOP, 1, "pop"},
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{0, IOOP, 0344, "inb"},
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{0, IOOP, 0345, "in"},
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{0, IOOP, 0345, "inw"},
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{0, IOOP, 0346, "outb"},
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{0, IOOP, 0347, "out"},
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{0, IOOP, 0347, "outw"},
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{0, ADDOP, 000, "addb"},
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{0, ADDOP, 001, "add"},
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{0, ADDOP, 010, "orb"},
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{0, ADDOP, 011, "or"},
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{0, ADDOP, 020, "adcb"},
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{0, ADDOP, 021, "adc"},
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{0, ADDOP, 030, "sbbb"},
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{0, ADDOP, 031, "sbb"},
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{0, ADDOP, 040, "andb"},
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{0, ADDOP, 041, "and"},
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{0, ADDOP, 050, "subb"},
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{0, ADDOP, 051, "sub"},
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{0, ADDOP, 060, "xorb"},
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{0, ADDOP, 061, "xor"},
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{0, ADDOP, 070, "cmpb"},
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{0, ADDOP, 071, "cmp"},
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{0, ROLOP, 000, "rolb"},
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{0, ROLOP, 001, "rol"},
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{0, ROLOP, 010, "rorb"},
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{0, ROLOP, 011, "ror"},
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{0, ROLOP, 020, "rclb"},
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{0, ROLOP, 021, "rcl"},
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{0, ROLOP, 030, "rcrb"},
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{0, ROLOP, 031, "rcr"},
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{0, ROLOP, 040, "salb"},
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{0, ROLOP, 040, "shlb"},
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{0, ROLOP, 041, "sal"},
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{0, ROLOP, 041, "shl"},
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{0, ROLOP, 050, "shrb"},
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{0, ROLOP, 051, "shr"},
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{0, ROLOP, 070, "sarb"},
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{0, ROLOP, 071, "sar"},
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{0, INCOP, 000, "incb"},
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{0, INCOP, 001, "inc"},
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{0, INCOP, 010, "decb"},
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{0, INCOP, 011, "dec"},
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{0, NOTOP, 020, "notb"},
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{0, NOTOP, 021, "not"},
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{0, NOTOP, 030, "negb"},
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{0, NOTOP, 031, "neg"},
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{0, NOTOP, 040, "mulb"},
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{0, NOTOP, 041, "mul"},
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{0, NOTOP, 050, "imulb"},
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{0, IMUL, 051, "imul"}, /* for 80286 */
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{0, NOTOP, 060, "divb"},
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{0, NOTOP, 061, "div"},
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{0, NOTOP, 070, "idivb"},
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{0, NOTOP, 071, "idiv"},
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{0, CALLOP, 020+(0350<<8), "call"},
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{0, CALLOP, 040+(0351<<8), "jmp"},
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{0, CALFOP, 030+(0232<<8), "callf"},
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{0, CALFOP, 050+(0352<<8), "jmpf"},
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{0, LEAOP, 0215, "lea"},
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{0, LEAOP, 0304, "les"},
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{0, LEAOP, 0305, "lds"},
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{0, ESC, 0, "esc"},
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{0, INT, 0, "int"},
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{0, RET, 0303, "ret"},
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{0, RET, 0313, "retf"},
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{0, XCHG, 0, "xchgb"},
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{0, XCHG, 1, "xchg"},
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{0, TEST, 0, "testb"},
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{0, TEST, 1, "test"},
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{0, MOV, 0, "movb"},
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{0, MOV, 1, "mov"},
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{0, MOV, 1, "movw"},
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/* Intel 8087 coprocessor keywords */
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{0, ST, 0, "st"},
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{0, FNOOP, FESC+1+(0xF0<<8), "f2xm1"},
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{0, FNOOP, FESC+1+(0xE1<<8), "fabs"},
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{0, FNOOP, FESC+1+(0xE0<<8), "fchs"},
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{0, FNOOP, FESC+3+(0xE2<<8), "fclex"},
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{0, FNOOP, FESC+6+(0xD9<<8), "fcompp"},
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{0, FNOOP, FESC+1+(0xF6<<8), "fdecstp"},
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{0, FNOOP, FESC+3+(0xE1<<8), "fdisi"},
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{0, FNOOP, FESC+3+(0xE0<<8), "feni"},
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{0, FNOOP, FESC+1+(0xF7<<8), "fincstp"},
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{0, FNOOP, FESC+3+(0xE3<<8), "finit"},
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{0, FNOOP, FESC+1+(0xE8<<8), "fld1"},
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{0, FNOOP, FESC+1+(0xEA<<8), "fldl2e"},
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{0, FNOOP, FESC+1+(0xE9<<8), "fldl2t"},
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{0, FNOOP, FESC+1+(0xEC<<8), "fldlg2"},
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{0, FNOOP, FESC+1+(0xED<<8), "fldln2"},
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{0, FNOOP, FESC+1+(0xEB<<8), "fldpi"},
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{0, FNOOP, FESC+1+(0xEE<<8), "fldz"},
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{0, FNOOP, FESC+1+(0xD0<<8), "fnop"},
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{0, FNOOP, FESC+1+(0xF3<<8), "fpatan"},
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{0, FNOOP, FESC+1+(0xF8<<8), "fprem"},
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{0, FNOOP, FESC+1+(0xF2<<8), "fptan"},
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{0, FNOOP, FESC+1+(0xFC<<8), "frndint"},
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{0, FNOOP, FESC+1+(0xFD<<8), "fscale"},
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{0, FNOOP, FESC+1+(0xFA<<8), "fsqrt"},
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{0, FNOOP, FESC+7+(0xE0<<8), "fstswax"}, /* 80287 */
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{0, FNOOP, FESC+1+(0xE4<<8), "ftst"},
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{0, FNOOP, FESC+1+(0xE5<<8), "fxam"},
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{0, FNOOP, FESC+1+(0xF4<<8), "fxtract"},
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{0, FNOOP, FESC+1+(0xF1<<8), "fyl2x"},
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{0, FNOOP, FESC+1+(0xF9<<8), "fyl2pi"},
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{0, FMEM, FESC+6+(0<<11), "fiadds"},
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{0, FMEM, FESC+2+(0<<11), "fiaddl"},
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{0, FMEM, FESC+0+(0<<11), "fadds"},
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{0, FMEM, FESC+4+(0<<11), "faddd"},
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{0, FMEM, FESC+7+(4<<11), "fbld"},
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{0, FMEM, FESC+7+(6<<11), "fbstp"},
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{0, FMEM, FESC+6+(2<<11), "ficoms"},
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{0, FMEM, FESC+2+(2<<11), "ficoml"},
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{0, FMEM, FESC+0+(2<<11), "fcoms"},
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{0, FMEM, FESC+4+(2<<11), "fcomd"},
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{0, FMEM, FESC+6+(3<<11), "ficomps"},
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{0, FMEM, FESC+2+(3<<11), "ficompl"},
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{0, FMEM, FESC+0+(3<<11), "fcomps"},
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{0, FMEM, FESC+4+(3<<11), "fcompd"},
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{0, FMEM, FESC+6+(6<<11), "fidivs"},
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{0, FMEM, FESC+2+(6<<11), "fidivl"},
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{0, FMEM, FESC+0+(6<<11), "fdivs"},
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{0, FMEM, FESC+4+(6<<11), "fdivd"},
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{0, FMEM, FESC+6+(7<<11), "fidivrs"},
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{0, FMEM, FESC+2+(7<<11), "fidivrl"},
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{0, FMEM, FESC+0+(7<<11), "fdivrs"},
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{0, FMEM, FESC+4+(7<<11), "fdivrd"},
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{0, FMEM, FESC+7+(5<<11), "fildq"},
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{0, FMEM, FESC+7+(0<<11), "filds"},
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{0, FMEM, FESC+3+(0<<11), "fildl"},
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{0, FMEM, FESC+1+(0<<11), "flds"},
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{0, FMEM, FESC+5+(0<<11), "fldd"},
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{0, FMEM, FESC+3+(5<<11), "fldx"},
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{0, FMEM, FESC+1+(5<<11), "fldcw"},
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{0, FMEM, FESC+1+(4<<11), "fldenv"},
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{0, FMEM, FESC+6+(1<<11), "fimuls"},
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{0, FMEM, FESC+2+(1<<11), "fimull"},
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{0, FMEM, FESC+0+(1<<11), "fmuls"},
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{0, FMEM, FESC+4+(1<<11), "fmuld"},
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{0, FMEM, FESC+5+(4<<11), "frstor"},
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{0, FMEM, FESC+5+(6<<11), "fsave"},
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{0, FMEM, FESC+7+(2<<11), "fists"},
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{0, FMEM, FESC+3+(2<<11), "fistl"},
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{0, FMEM, FESC+1+(2<<11), "fsts"},
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{0, FMEM, FESC+5+(2<<11), "fstd"},
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{0, FMEM, FESC+7+(7<<11), "fistpq"},
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{0, FMEM, FESC+7+(3<<11), "fistps"},
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{0, FMEM, FESC+3+(3<<11), "fistpl"},
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{0, FMEM, FESC+1+(3<<11), "fstps"},
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{0, FMEM, FESC+5+(3<<11), "fstpd"},
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{0, FMEM, FESC+3+(7<<11), "fstpx"},
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{0, FMEM, FESC+1+(7<<11), "fstcw"},
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{0, FMEM, FESC+1+(6<<11), "fstenv"},
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{0, FMEM, FESC+5+(7<<11), "fstsw"},
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{0, FMEM, FESC+6+(4<<11), "fisubs"},
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{0, FMEM, FESC+2+(4<<11), "fisubl"},
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{0, FMEM, FESC+0+(4<<11), "fsubs"},
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{0, FMEM, FESC+4+(4<<11), "fsubd"},
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{0, FMEM, FESC+6+(5<<11), "fisubrs"},
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{0, FMEM, FESC+2+(5<<11), "fisubrl"},
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{0, FMEM, FESC+0+(5<<11), "fsubrs"},
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{0, FMEM, FESC+4+(5<<11), "fsubrd"},
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{0, FST_I, FESC+1+(0xC0<<8), "fld"},
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{0, FST_I, FESC+5+(0xD0<<8), "fst"},
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{0, FST_I, FESC+5+(0xC8<<8), "fstp"},
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{0, FST_I, FESC+1+(0xC8<<8), "fxch"},
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{0, FST_I, FESC+0+(0xD0<<8), "fcom"},
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{0, FST_I, FESC+0+(0xD8<<8), "fcomp"},
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{0, FST_I, FESC+5+(0xC0<<8), "ffree"},
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{0, FST_ST, FESC+0+(0xC0<<8), "fadd"},
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{0, FST_ST, FESC+2+(0xC0<<8), "faddp"},
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{0, FST_ST2, FESC+0+(0xF0<<8), "fdiv"},
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{0, FST_ST2, FESC+2+(0xF0<<8), "fdivp"},
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{0, FST_ST2, FESC+0+(0xF8<<8), "fdivr"},
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{0, FST_ST2, FESC+2+(0xF8<<8), "fdivrp"},
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{0, FST_ST, FESC+0+(0xC8<<8), "fmul"},
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{0, FST_ST, FESC+2+(0xC8<<8), "fmulp"},
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{0, FST_ST2, FESC+0+(0xE0<<8), "fsub"},
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{0, FST_ST2, FESC+2+(0xE0<<8), "fsubp"},
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{0, FST_ST2, FESC+0+(0xE8<<8), "fsubr"},
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{0, FST_ST2, FESC+2+(0xE8<<8), "fsubrp"},
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/* 80286 keywords */
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{0, NOOP_1, 0140, "pusha"},
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{0, NOOP_1, 0141, "popa"},
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{0, NOOP_1, 0154, "insb"},
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{0, NOOP_1, 0155, "ins"},
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{0, NOOP_1, 0155, "insw"},
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{0, NOOP_1, 0156, "outsb"},
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{0, NOOP_1, 0157, "outs"},
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{0, NOOP_1, 0157, "outsw"},
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{0, ARPLOP, 0143, "arpl"},
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{0, ENTER, 0310, "enter"},
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{0, NOOP_1, 0311, "leave"},
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{0, LEAOP, 0142, "bound"},
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{0, NOOP_2, 017+06<<8, "clts"},
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{0, EXTOP, 0002, "lar"},
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{0, EXTOP, 0003, "lsl"},
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{0, EXTOP1, 0021, "lgdt"},
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{0, EXTOP1, 0001, "sgdt"},
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{0, EXTOP1, 0031, "lidt"},
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{0, EXTOP1, 0011, "sidt"},
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{0, EXTOP1, 0020, "lldt"},
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{0, EXTOP1, 0000, "sldt"},
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{0, EXTOP1, 0030, "ltr"},
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{0, EXTOP1, 0010, "str"},
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{0, EXTOP1, 0061, "lmsw"},
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{0, EXTOP1, 0041, "smsw"},
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{0, EXTOP1, 0050, "verw"},
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{0, EXTOP1, 0040, "verr"},
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