c72eaef8ee
--HG-- branch : dtrg-videocore rename : plat/rpi/libsys/pi_user_to_phys.s => plat/rpi/libsys/pi_fast_mode.s
185 lines
3 KiB
ArmAsm
185 lines
3 KiB
ArmAsm
#
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/*
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* Raspberry Pi support library for the ACK
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* © 2013 David Given
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* This file is redistributable under the terms of the 3-clause BSD license.
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* See the file 'Copying' in the root of the distribution for the full text.
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*/
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#include "libsysasm.h"
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.sect .text
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! Because of the low system clock rate, this baud rate might be inaccurate
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! So be careful with your serial/terminal, some adjustment may be necessary.
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TARGET_BAUD_RATE = 115200
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GPFSEL1 = 0x7e200004
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GPSET0 = 0x7e20001C
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GPCLR0 = 0x7e200028
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GPPUD = 0x7e200094
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GPPUDCLK0 = 0x7e200098
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AUX_ENABLES = 0x7e215004
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AUX_MU_IO_REG = 0x7e215040
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AUX_MU_IER_REG = 0x7e215044
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AUX_MU_IIR_REG = 0x7e215048
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AUX_MU_LCR_REG = 0x7e21504C
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AUX_MU_MCR_REG = 0x7e215050
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AUX_MU_LSR_REG = 0x7e215054
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AUX_MU_MSR_REG = 0x7e215058
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AUX_MU_SCRATCH = 0x7e21505C
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AUX_MU_CNTL_REG = 0x7e215060
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AUX_MU_STAT_REG = 0x7e215064
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AUX_MU_BAUD_REG = 0x7e215068
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! Sets up the mini UART for use as a console.
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.define _pi_init_uart
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_pi_init_uart:
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! Configure TX and RX GPIO pins for Mini Uart function.
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mov r1, #GPFSEL1
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ld r0, (r1)
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and r0, #~[7<<12]
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or r0, #2<<12
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and r0, #~[7<<15]
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or r0, #2<<15
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st r0, (r1)
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mov r1, #GPPUD
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mov r0, #0
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st r0, (r1)
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delay1:
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add r0, #1
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cmp r0, #150
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b.ne delay1
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mov r1, #GPPUDCLK0
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mov r0, #[1<<14]|[1<<15]
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st r0, (r1)
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mov r0, #0
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delay2:
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add r0, #1
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cmp r0, #150
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b.ne delay2
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mov r1, #GPPUDCLK0
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mov r0, #0
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st r0, (r1)
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! Set up serial port
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mov r1, #AUX_ENABLES
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mov r0, #1
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st r0, (r1)
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mov r1, #AUX_MU_IER_REG
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mov r0, #0
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st r0, (r1)
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mov r1, #AUX_MU_CNTL_REG
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mov r0, #0
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st r0, (r1)
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mov r1, #AUX_MU_LCR_REG
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mov r0, #3
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st r0, (r1)
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mov r1, #AUX_MU_MCR_REG
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mov r0, #0
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st r0, (r1)
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mov r1, #AUX_MU_IER_REG
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mov r0, #0
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st r0, (r1)
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mov r1, #AUX_MU_IIR_REG
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mov r0, #0xC6
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st r0, (r1)
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mov r1, #AUX_MU_BAUD_REG
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ld r0, _pi_clock_speed
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mov r2, #TARGET_BAUD_RATE*8
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divu r0, r0, r2
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sub r0, #1
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st r0, (r1)
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mov r1, #AUX_MU_LCR_REG
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mov r0, #3
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st r0, (r1)
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mov r1, #AUX_MU_CNTL_REG
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mov r0, #3
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st r0, (r1)
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! Mark the uart as being initialised.
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mov r0, #1
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stb r0, __uart_status
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b lr
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! Send a single byte.
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.define __sys_rawwrite
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__sys_rawwrite:
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ldb r0, __uart_status
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b.eq r0, #0, 1f
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ld r0, (sp)
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mov r1, #AUX_MU_LSR_REG
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! loop until space available in Tx buffer
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sendwait:
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ld r2, (r1)
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and r2, #0x20
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cmp r2, #0x20
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b.ne sendwait
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mov r1, #AUX_MU_IO_REG
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stb r0, (r1)
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1:
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b lr
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! Poll to see if there's incoming data available.
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.define __sys_rawpoll
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.define __sys_rawpoll
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__sys_rawpoll:
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ldb r0, __uart_status
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b.eq r0, #0, 1b
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mov r1, #AUX_MU_LSR_REG
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ld r0, (r1)
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and r0, #0x1 ! 0 if no data, 1 if data
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1:
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b lr
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! Receive a single byte.
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.define __sys_rawread
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__sys_rawread:
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ldb r0, __uart_status
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b.eq r0, #0, 1b
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! receive 1 byte (returned in r0)
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mov r1, #AUX_MU_LSR_REG
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mov r2, #AUX_MU_IO_REG
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! loop until char available
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recvwait:
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ld r3, (r1)
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and r3, #0x1
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b.ne r3, #0x1, recvwait
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ldb r0, (r2)
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1:
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b lr
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.comm __uart_status, 1
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.sect .data
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.define _pi_clock_speed
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! System clock is running directly off the 19.2MHz crystal at initial reset
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_pi_clock_speed:
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.data4 19200000
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