123 lines
		
	
	
	
		
			2.5 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			123 lines
		
	
	
	
		
			2.5 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| #define RCSID3 "$Header$"
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| 
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| /*
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|  * Motorola 6805 keywords
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|  */
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| /*
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|  * The X register
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|  */
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| 0,	X,		0,		"x",
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| /*
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|  * Bit test and branch
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|  */
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| 0,	BBRANCH,	0x00,		"brset",
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| 0,	BBRANCH,	0x01,		"brclr",
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| /*
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|  * Bit manipulation
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|  */
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| 0,	BIT,		0x10,		"bset",
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| 0,	BIT,		0x11,		"bclr",
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| /*
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|  * Branches
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|  */
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| 0,	BRANCH,		0x20,		"bra",
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| 0,	BRANCH,		0x21,		"brn",
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| 0,	BRANCH,		0x22,		"bhi",
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| 0,	BRANCH,		0x23,		"bls",
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| 0,	BRANCH,		0x24,		"bcc",
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| 0,	BRANCH,		0x25,		"bcs",
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| 0,	BRANCH,		0x26,		"bne",
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| 0,	BRANCH,		0x27,		"beq",
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| 0,	BRANCH,		0x28,		"bhcc",
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| 0,	BRANCH,		0x29,		"bhcs",
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| 0,	BRANCH,		0x2a,		"bpl",
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| 0,	BRANCH,		0x2b,		"bmi",
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| 0,	BRANCH,		0x2c,		"bmc",
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| 0,	BRANCH,		0x2d,		"bms",
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| 0,	BRANCH,		0x2e,		"bil",
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| 0,	BRANCH,		0x2f,		"bih",
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| /*
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|  * Read modify write on anything but registers
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|  */
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| 0,	RMR,		0x30,		"neg",
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| 0,	RMR,		0x33,		"com",
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| 0,	RMR,		0x34,		"lsr",
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| 0,	RMR,		0x36,		"ror",
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| 0,	RMR,		0x36,		"asr",
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| 0,	RMR,		0x38,		"lsl",
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| 0,	RMR,		0x39,		"rol",
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| 0,	RMR,		0x3a,		"dec",
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| 0,	RMR,		0x3c,		"inc",
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| 0,	RMR,		0x3d,		"tst",
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| 0,	RMR,		0x3f,		"clr",
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| /*
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|  * Implied stuff
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|  */
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| 0,	NOARG,		0x80,		"rti",
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| 0,	NOARG,		0x81,		"rts",
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| 0,	NOARG,		0x83,		"swi",
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| 0,	NOARG,		0x97,		"tax",
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| 0,	NOARG,		0x98,		"clc",
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| 0,	NOARG,		0x99,		"sec",
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| 0,	NOARG,		0x9a,		"cli",
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| 0,	NOARG,		0x9b,		"sei",
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| 0,	NOARG,		0x9c,		"rsp",
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| 0,	NOARG,		0x9d,		"nop",
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| 0,	NOARG,		0x9f,		"txa",
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| /*
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|  * Register memory.
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|  * Warning. Some imediate opcodes excluded in parser actions.
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|  */
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| 0,	RM,		0xa0,		"sub",
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| 0,	RM,		0xa1,		"cmp",
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| 0,	RM,		0xa2,		"sbc",
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| 0,	RM,		0xa3,		"cpx",
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| 0,	RM,		0xa4,		"and",
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| 0,	RM,		0xa5,		"bit",
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| 0,	RM,		0xa6,		"lda",
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| 0,	RM,		0xa7,		"sta",
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| 0,	RM,		0xa8,		"eor",
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| 0,	RM,		0xa9,		"adc",
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| 0,	RM,		0xaa,		"ora",
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| 0,	RM,		0xab,		"add",
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| 0,	RM,		0xac,		"jmp",
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| 0,	BRANCH,		0xad,		"bsr",
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| 0,	RM,		0xad,		"jsr",
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| 0,	RM,		0xae,		"ldx",
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| 0,	RM,		0xaf,		"stx",
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| /*
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|  * Branch synonyms
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|  */
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| 0,	BRANCH,		0x24,		"bhs",	/* bcc */
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| 0,	BRANCH,		0x25,		"blo",	/* bcs */
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| /*
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|  * Brain damaged concatenated opcodes for RMR on registers
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|  */
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| 0,	NOARG,		0x40,		"nega",
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| 0,	NOARG,		0x43,		"coma",
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| 0,	NOARG,		0x44,		"lsra",
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| 0,	NOARG,		0x46,		"rora",
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| 0,	NOARG,		0x47,		"asra",
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| 0,	NOARG,		0x48,		"lsla",
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| 0,	NOARG,		0x49,		"rola",
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| 0,	NOARG,		0x4a,		"deca",
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| 0,	NOARG,		0x4c,		"inca",
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| 0,	NOARG,		0x4d,		"tsta",
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| 0,	NOARG,		0x4f,		"clra",
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| 0,	NOARG,		0x50,		"negx",
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| 0,	NOARG,		0x53,		"comx",
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| 0,	NOARG,		0x54,		"lsrx",
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| 0,	NOARG,		0x56,		"rorx",
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| 0,	NOARG,		0x57,		"asrx",
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| 0,	NOARG,		0x58,		"lslx",
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| 0,	NOARG,		0x59,		"rolx",
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| 0,	NOARG,		0x5a,		"decx",
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| 0,	NOARG,		0x5c,		"incx",
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| 0,	NOARG,		0x5d,		"tstx",
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| 0,	NOARG,		0x5f,		"clrx",
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| /*
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|  * CMOS support
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|  */
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| 0,	CMOS,		0,		".cmos",
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| 0,	CMOS,		0x8e,		"stop",
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| 0,	CMOS,		0x8f,		"wait",
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