95 lines
1.5 KiB
ArmAsm
95 lines
1.5 KiB
ArmAsm
.define _Swi, _Swix, _bbc_get, _bbc_vduw, _bbc_vdu
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.sect .text
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! Swi(code, regpt)
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_Swi:
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ADR R11,_100
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LDR R10,[R11]
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LDR R9,[R12]
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AND R10,R10,#0xFF000000
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AND R9,R9,#0xFFFFFF
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ORR R10,R10,R9
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STR R10,[R11]
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LDR R11,[R12,#4] ! PT TO REGS
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STMFD R12<,{R4,R5,R6,R7}
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LDR R0,[R11,#0]
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LDR R1,[R11,#4]
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LDR R2,[R11,#8]
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LDR R3,[R11,#12]
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LDR R4,[R11,#16]
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LDR R5,[R11,#20]
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LDR R6,[R11,#24]
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LDR R7,[R11,#28]
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LDR R8,[R11,#32]
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LDR R9,[R11,#36]
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_100:
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SWI 0
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STR R0,[R11,#0]
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STR R1,[R11,#4]
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STR R2,[R11,#8]
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STR R3,[R11,#12]
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STR R4,[R11,#16]
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STR R5,[R11,#20]
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STR R6,[R11,#24]
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STR R7,[R11,#28]
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STR R8,[R11,#32]
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STR R9,[R11,#36]
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LDMFD R12<,{R4,R5,R6,R7}
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MOV.S R15,R14
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_Swix:
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ADR R11,_101
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LDR R10,[R11]
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LDR R9,[R12]
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AND R10,R10,#0xFF000000
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AND R9,R9,#0xFFFFFF
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ORR R10,R10,R9
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ORR R10,R10,#0x20000
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STR R10,[R11]
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LDR R11,[R12,#4]
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STMFD R12<,{R4,R5,R6,R7}
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LDR R0,[R11,#0]
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LDR R1,[R11,#4]
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LDR R2,[R11,#8]
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LDR R3,[R11,#12]
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LDR R4,[R11,#16]
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LDR R5,[R11,#20]
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LDR R6,[R11,#24]
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LDR R7,[R11,#28]
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LDR R8,[R11,#32]
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LDR R9,[R11,#36]
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_101:
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SWI 0
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STR R0,[R11,#0]
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STR R1,[R11,#4]
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STR R2,[R11,#8]
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STR R3,[R11,#12]
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STR R4,[R11,#16]
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STR R5,[R11,#20]
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STR R6,[R11,#24]
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STR R7,[R11,#28]
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STR R8,[R11,#32]
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STR R9,[R11,#36]
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MOV.VC R0, #0
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LDMFD R12<,{R4,R5,R6,R7}
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MOV.S R15,R14
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! the rest is for Acorn compatibility
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_bbc_get:
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SWI 4 ! READC
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MOV.S R15,R14
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_bbc_vduw:
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LDR R0,[R12]
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SWI 0 !WRITEC
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MOV R0,R0,LSR #8
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SWI 0
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MOV.S R15,R14
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_bbc_vdu:
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LDR R0,[R12]
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SWI 0
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MOV.S R15,R14
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