3f3bf1e164
Calls like `debug("something\n", 0, 0, 0, 0)` cause clang warnings,
because debug() is a macro that passes its arguments to printf(), and
clang warns about extra 0s to printf(). Silence the warnings by
hiding the printf() in a new function do_debug(). The code still
passes extra 0s to printf(), but clang can't warn.
Macros debug() and verbose() should use C99 __VA_ARGS__, so they don't
require the extra 0s; but ACK doesn't use __VA_ARGS__ yet.
Adjust some format strings for debug() or fatal(), or cast their
arguments, to match their types. I don't know whether uint32_t is
unsigned int or unsigned long, so I cast it to unsigned long, and
print it with "%lx".
In util/led/sym.c, #include "save.h" to declare savechar(), and use
parentheses to silence a clang warning in hash().
611 lines
15 KiB
C
611 lines
15 KiB
C
/*
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* (c) copyright 1987 by the Vrije Universiteit, Amsterdam, The Netherlands.
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* See the copyright notice in the ACK home directory, in the file "Copyright".
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*/
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#ifndef lint
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static char rcsid[] = "$Id$";
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#endif
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#include <stdlib.h>
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#include <stdio.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <assert.h>
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#include "out.h"
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#include "const.h"
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#include "debug.h"
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#include "defs.h"
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#include "orig.h"
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#include "sym.h"
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#include "relocate.h"
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#define UBYTE(x) ((x)&BYTEMASK)
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static uint16_t read2(char* addr, int type)
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{
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unsigned short word0, word1;
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if (type & RELBR)
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return (UBYTE(addr[0]) << WIDTH) + UBYTE(addr[1]);
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else
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return (UBYTE(addr[1]) << WIDTH) + UBYTE(addr[0]);
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}
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static uint32_t read4(char* addr, int type)
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{
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unsigned short word0, word1;
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if (type & RELBR)
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{
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word0 = (UBYTE(addr[0]) << WIDTH) + UBYTE(addr[1]);
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word1 = (UBYTE(addr[2]) << WIDTH) + UBYTE(addr[3]);
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}
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else
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{
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word0 = (UBYTE(addr[1]) << WIDTH) + UBYTE(addr[0]);
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word1 = (UBYTE(addr[3]) << WIDTH) + UBYTE(addr[2]);
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}
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if (type & RELWR)
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return ((long)word0 << (2 * WIDTH)) + word1;
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else
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return ((long)word1 << (2 * WIDTH)) + word0;
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}
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/* VideoCore 4 fixups are complex as we need to patch the instruction in
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* one of several different ways (depending on what the instruction is).
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*/
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static uint32_t get_vc4_valu(char* addr)
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{
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uint16_t opcode = read2(addr, 0);
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if ((opcode & 0xff00) == 0xe700)
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{
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/* ld<w> rd, $+o: [1110 0111 ww 0 d:5] [11111 o:27]
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* st<w> rd, $+o: [1110 0111 ww 1 d:5] [11111 o:27]
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*/
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int32_t value = read4(addr + 2, 0);
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value &= 0x07ffffff;
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value = value << 5 >> 5;
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return value;
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}
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if ((opcode & 0xf080) == 0x9000)
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{
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/* b<cc> $+o*2: [1001 cccc 0ooo oooo] [oooo oooo oooo oooo]
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* Yes, big-endian (the first 16 bits is the MSB).
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*/
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uint32_t value = read4(addr, RELWR);
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value &= 0x007fffff;
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value = value << 9 >> 9;
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value *= 2;
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return value;
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}
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if ((opcode & 0xf080) == 0x9080)
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{
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/* bl $+o*2: [1001 oooo 1ooo oooo] [oooo oooo oooo oooo]
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* Yes, big-endian (the first 16 bits is the MSB).
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* (Note that o is split.)
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*/
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int32_t value = read4(addr, RELWR);
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int32_t lov = value & 0x007fffff;
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int32_t hiv = value & 0x0f000000;
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value = lov | (hiv >> 1);
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value = value << 5 >> 5;
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value *= 2;
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return value;
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}
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if ((opcode & 0xffe0) == 0xe500)
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{
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/* lea: [1110 0101 000 d:5] [o:32] */
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return read4(addr + 2, 0);
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}
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assert(0 && "unrecognised VC4 instruction");
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}
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static bool is_powerpc_memory_op(uint32_t opcode)
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{
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/* Tests for any PowerPC memory indirection instruction (or
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* addi) where the payload is a *signed* 16-bit value. */
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switch ((opcode & 0xfc000000) >> 26)
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{
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case 14: /* addi */
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case 34: /* lbz */
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case 48: /* lfs */
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case 50: /* lfd */
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case 42: /* lha */
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case 40: /* lhz */
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case 32: /* lwz */
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case 38: /* stb */
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case 52: /* stfs */
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case 54: /* stfd */
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case 44: /* sth */
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case 36: /* stw */
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return true;
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}
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return false;
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}
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/* PowerPC fixups are complex as we need to patch up to the next two
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* instructions in one of several different ways, depending on what the
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* instructions area.
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*/
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static uint32_t get_powerpc_valu(char* addr, uint16_t type)
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{
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uint32_t opcode1 = read4(addr + 0, type);
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uint32_t opcode2 = read4(addr + 4, type);
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if ((opcode1 & 0xfc000000) == 0x48000000)
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{
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/* branch instruction */
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return opcode1 & 0x03fffffd;
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}
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else if (((opcode1 & 0xfc1f0000) == 0x3c000000) && ((opcode2 & 0xfc000000) == 0x60000000))
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{
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/* addis / ori instruction pair */
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return ((opcode1 & 0xffff) << 16) | (opcode2 & 0xffff);
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}
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else if (((opcode1 & 0xfc1f0000) == 0x3c000000) && is_powerpc_memory_op(opcode2))
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{
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/* addis / memoryop instruction pair */
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uint16_t hi = opcode1 & 0xffff;
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uint16_t lo = opcode2 & 0xffff;
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/* Undo the sign adjustment (see mach/powerpc/as/mach5.c). */
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if (lo > 0x7fff)
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hi--;
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return ((hi << 16) | lo);
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}
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fatal(
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"Don't know how to read from PowerPC fixup on instructions 0x%08lx+0x%08lx",
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(unsigned long)opcode1, (unsigned long)opcode2);
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}
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/* RELOPPC_LIS stores a signed 26-bit offset in the low bits. */
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static uint32_t get_lis_valu(char* addr, uint16_t type)
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{
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uint32_t valu = read4(addr, type) & 0x03ffffff;
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if (valu & 0x02000000)
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valu |= 0xfc000000; /* sign extension */
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return valu;
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}
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/* RELOMIPS is used for j and b instructions only. */
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static uint32_t get_mips_valu(char* addr)
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{
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uint32_t value = read4(addr, 0);
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switch (value >> 26)
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{
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case 2: /* j */
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case 3: /* jal */
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case 29: /* jalx */
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/* Unsigned 26-bit payload. */
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value = value & ((1 << 26) - 1);
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break;
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default: /* assume everything else is a b, there are lots */
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/* Signed 16-bit payload. */
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value = ((int32_t)value << 16) >> 16;
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break;
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}
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/* The value has two implicit zero bits on the bottom. */
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value <<= 2;
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return value;
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}
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/*
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* The bits in type indicate how many bytes the value occupies and what
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* significance should be attributed to each byte.
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*/
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static uint32_t getvalu(char* addr, uint16_t type)
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{
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switch (type & RELSZ)
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{
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case RELO1:
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return UBYTE(addr[0]);
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case RELO2:
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case RELO2HI:
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case RELO2HISAD:
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return read2(addr, type);
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case RELO4:
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return read4(addr, type);
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case RELOPPC:
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return get_powerpc_valu(addr, type);
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case RELOPPC_LIS:
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return get_lis_valu(addr, type);
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case RELOVC4:
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return get_vc4_valu(addr);
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case RELOMIPS:
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return get_mips_valu(addr);
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default:
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fatal("can't read relocation type %x", type & RELSZ);
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}
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/* NOTREACHED */
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}
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static void write2(uint16_t valu, char* addr, int type)
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{
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unsigned short word0, word1;
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if (type & RELBR)
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{
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addr[0] = valu >> WIDTH;
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addr[1] = valu;
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}
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else
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{
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addr[0] = valu;
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addr[1] = valu >> WIDTH;
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}
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}
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static void write4(uint32_t valu, char* addr, int type)
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{
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unsigned short word0, word1;
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if (type & RELWR)
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{
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word0 = valu >> (2 * WIDTH);
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word1 = valu;
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}
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else
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{
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word0 = valu;
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word1 = valu >> (2 * WIDTH);
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}
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if (type & RELBR)
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{
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addr[0] = word0 >> WIDTH;
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addr[1] = word0;
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addr[2] = word1 >> WIDTH;
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addr[3] = word1;
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}
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else
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{
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addr[0] = word0;
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addr[1] = word0 >> WIDTH;
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addr[2] = word1;
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addr[3] = word1 >> WIDTH;
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}
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}
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/* VideoCore 4 fixups are complex as we need to patch the instruction in
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* one of several different ways (depending on what the instruction is).
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*/
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static void put_vc4_valu(char* addr, uint32_t value)
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{
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uint16_t opcode = read2(addr, 0);
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if ((opcode & 0xff00) == 0xe700)
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{
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/* ld<w> rd, o, (pc): [1110 0111 ww 0 d:5] [11111 o:27]
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* st<w> rd, o, (pc): [1110 0111 ww 1 d:5] [11111 o:27]
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*/
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uint32_t v = read4(addr + 2, 0);
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v &= 0xf8000000;
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v |= value & 0x07ffffff;
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write4(v, addr + 2, 0);
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}
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else if ((opcode & 0xf080) == 0x9000)
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{
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/* b<cc> dest: [1001 cccc 0ooo oooo] [oooo oooo oooo oooo]
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* Yes, big-endian (the first 16 bits is the MSB).
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*/
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uint32_t v = read4(addr, RELWR);
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v &= 0xff800000;
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v |= (value / 2) & 0x007fffff;
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write4(v, addr, RELWR);
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}
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else if ((opcode & 0xf080) == 0x9080)
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{
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/* bl dest: [1001 oooo 1ooo oooo] [oooo oooo oooo oooo]
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* Yes, big-endian (the first 16 bits is the MSB).
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* (Note that o is split.)
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*/
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uint32_t v = read4(addr, RELWR);
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uint32_t lovalue = (value / 2) & 0x007fffff;
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uint32_t hivalue = (value / 2) & 0x07800000;
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v &= 0xf0800000;
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v |= lovalue | (hivalue << 1);
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write4(v, addr, RELWR);
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}
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else if ((opcode & 0xffe0) == 0xe500)
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{
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/* lea: [1110 0101 000 d:5] [o:32] */
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write4(value, addr + 2, 0);
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}
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else
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assert(0 && "unrecognised VC4 instruction");
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}
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/* PowerPC fixups are complex as we need to patch up to the next two
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* instructions in one of several different ways, depending on what the
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* instructions area.
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*/
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static void put_powerpc_valu(char* addr, uint32_t value, uint16_t type)
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{
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uint32_t opcode1 = read4(addr + 0, type);
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uint32_t opcode2 = read4(addr + 4, type);
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if ((opcode1 & 0xfc000000) == 0x48000000)
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{
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/* branch instruction */
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uint32_t i = opcode1 & ~0x03fffffd;
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i |= value & 0x03fffffd;
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write4(i, addr, type);
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}
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else if (((opcode1 & 0xfc1f0000) == 0x3c000000) && ((opcode2 & 0xfc000000) == 0x60000000))
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{
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/* addis / ori instruction pair */
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uint16_t hi = value >> 16;
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uint16_t lo = value & 0xffff;
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write4((opcode1 & 0xffff0000) | hi, addr + 0, type);
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write4((opcode2 & 0xffff0000) | lo, addr + 4, type);
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}
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else if (((opcode1 & 0xfc1f0000) == 0x3c000000) && is_powerpc_memory_op(opcode2))
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{
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/* addis / memoryop instruction pair */
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uint16_t hi = value >> 16;
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uint16_t lo = value & 0xffff;
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/* Apply the sign adjustment (see mach/powerpc/as/mach5.c). */
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if (lo > 0x7fff)
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hi++;
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write4((opcode1 & 0xffff0000) | hi, addr + 0, type);
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write4((opcode2 & 0xffff0000) | lo, addr + 4, type);
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}
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else
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fatal(
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"Don't know how to write a PowerPC fixup to instructions 0x%08lx+0x%08lx",
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(unsigned long)opcode1, (unsigned long)opcode2);
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}
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/* Writes a PowerPC lis instruction. */
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static void put_lis_valu(char* addr, uint32_t value, uint16_t type)
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{
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uint32_t opcode, reg;
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uint16_t hi, lo;
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bool ha16;
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/* ha16 flag in high bit, register in next 5 bits */
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opcode = read4(addr, type);
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ha16 = opcode >> 31;
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reg = (opcode >> 26) & 0x1f;
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/*
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* Apply the sign adjustment if the ha16 flag is set and the
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* low half is a negative signed 16-bit integer.
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*/
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hi = value >> 16;
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lo = value & 0xffff;
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if (ha16 && lo > 0x7fff)
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hi++;
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/* Assemble lis reg, hi == addis reg, r0, hi. */
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opcode = (15 << 26) | (reg << 21) | (0 << 16) | hi;
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write4(opcode, addr, type);
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}
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/* RELOMIPS is used for j and b instructions only. */
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static void put_mips_valu(char* addr, uint32_t value)
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{
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uint32_t opcode = read4(addr, 0);
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/* The two bottom zero bits are implicit. */
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if (value & 3)
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fatal("invalid MIPS relocation value 0x%lx",
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(unsigned long)value);
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value >>= 2;
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switch (opcode >> 26)
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{
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case 2: /* j */
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case 3: /* jal */
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case 29: /* jalx */
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/* Unsigned 26-bit payload. */
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value = value & ((1 << 26) - 1);
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opcode = opcode & ~((1 << 26) - 1);
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break;
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default: /* assume everything else is a b, there are lots */
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/* Signed 16-bit payload. */
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value = value & ((1 << 16) - 1);
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opcode = opcode & ~((1 << 16) - 1);
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break;
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}
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write4(opcode | value, addr, 0);
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}
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/*
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* The bits in type indicate how many bytes the value occupies and what
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* significance should be attributed to each byte.
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* We do not check for overflow.
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*/
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static void putvalu(uint32_t valu, char* addr, uint16_t type)
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{
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switch (type & RELSZ)
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{
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case RELO1:
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addr[0] = valu;
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break;
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case RELO2:
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write2(valu, addr, type);
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break;
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case RELO2HI:
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write2(valu >> 16, addr, type);
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break;
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case RELO2HISAD:
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write2((valu >> 16) + !!(valu & 0x8000), addr, type);
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break;
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case RELO4:
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write4(valu, addr, type);
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break;
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case RELOPPC:
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put_powerpc_valu(addr, valu, type);
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break;
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case RELOPPC_LIS:
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put_lis_valu(addr, valu, type);
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break;
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case RELOVC4:
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put_vc4_valu(addr, valu);
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break;
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case RELOMIPS:
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put_mips_valu(addr, valu);
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break;
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default:
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fatal("can't write relocation type %x", type & RELSZ);
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}
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}
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extern struct outsect outsect[];
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extern struct orig relorig[];
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/*
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* There are two cases: `local' is an undefined external or common name,
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* or `local' is a section name.
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* First case: if the name has been defined in another module,
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* its value is known and can be added. Or_nami will be the
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* index of the name of the section in which this name was
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* defined. Otherwise we must change or_nami to the index of
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* this name in the name table of the output file and leave
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* its value unchanged.
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* Second case: we must update the value by the change
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* in position of the section of local.
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*/
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static unsigned addrelo(relo, names, valu_out) struct outrelo* relo;
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struct outname* names;
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long* valu_out; /* Out variable. */
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{
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register struct outname* local = &names[relo->or_nami];
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register unsigned short index = NLocals;
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register long valu = *valu_out;
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if ((local->on_type & S_SCT))
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{
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register int sectindex = (local->on_type & S_TYP) - S_MIN;
|
|
|
|
valu += relorig[sectindex].org_size;
|
|
valu += outsect[sectindex].os_base;
|
|
index += NGlobals + sectindex;
|
|
}
|
|
else
|
|
{
|
|
register struct outname* name;
|
|
extern int hash();
|
|
extern struct outname* searchname();
|
|
extern unsigned indexof();
|
|
extern struct outhead outhead;
|
|
|
|
name = searchname(local->on_mptr, hash(local->on_mptr));
|
|
if (name == (struct outname*)0)
|
|
fatal("name %s not found in pass 2", local->on_mptr);
|
|
if (ISCOMMON(name) || ISUNDEFINED(name))
|
|
{
|
|
debug("can't relocate from %s\n", local->on_mptr, 0, 0, 0);
|
|
index += indexof(name);
|
|
}
|
|
else
|
|
{
|
|
valu += name->on_valu;
|
|
if ((name->on_type & S_TYP) == S_ABS)
|
|
{
|
|
index += NGlobals + outhead.oh_nsect;
|
|
}
|
|
else
|
|
index += NGlobals + (name->on_type & S_TYP) - S_MIN;
|
|
}
|
|
}
|
|
*valu_out = valu;
|
|
return index;
|
|
}
|
|
|
|
/*
|
|
* This routine relocates a value in a section pointed to by `emit', of
|
|
* which the header is pointed to by `head'. Relocation is relative to the
|
|
* names in `names'; `relo' tells how to relocate.
|
|
*/
|
|
void relocate(struct outhead *head, char* emit, struct outname names[], struct outrelo *relo, long off)
|
|
{
|
|
long valu;
|
|
int sectindex = relo->or_sect - S_MIN;
|
|
extern struct outhead outhead;
|
|
uint32_t realaddress = outsect[sectindex].os_base + relo->or_addr
|
|
+ relorig[sectindex].org_size;
|
|
|
|
/*
|
|
* Pick up previous value at location to be relocated.
|
|
*/
|
|
valu = getvalu(emit + (relo->or_addr - off), relo->or_type);
|
|
debug("read relocation from 0x%08lx type 0x%x value 0x%08lx symbol %u\n",
|
|
(unsigned long)realaddress, relo->or_type, valu, relo->or_nami);
|
|
|
|
/*
|
|
* Or_nami is an index in the name table of the considered module.
|
|
* The name of which it is an index can be:
|
|
* - an undefined external or a common name
|
|
* - a section name
|
|
* - the first name outside! the name table (argh)
|
|
*/
|
|
if (relo->or_nami < head->oh_nname)
|
|
{
|
|
/* First two cases. */
|
|
relo->or_nami = addrelo(relo, names, &valu);
|
|
}
|
|
else
|
|
{
|
|
/*
|
|
* Third case: it is absolute. The relocation of absolute
|
|
* names is always 0. We only need to change the index.
|
|
*/
|
|
relo->or_nami = NLocals + NGlobals + outhead.oh_nsect;
|
|
}
|
|
|
|
/*
|
|
* If relocation is pc-relative, we had to update the value by
|
|
* the change in distance between the referencING and referencED
|
|
* section. We already added the origin of the referencED section;
|
|
* now we subtract the origin of the referencING section.
|
|
*/
|
|
if (relo->or_type & RELPC)
|
|
valu -= relorig[sectindex].org_size + outsect[sectindex].os_base;
|
|
|
|
/*
|
|
* Now put the value back.
|
|
*/
|
|
debug("written fixed up relocation to 0x%08lx type 0x%x value 0x%08lx\n",
|
|
(unsigned long)realaddress, relo->or_type, valu, 0);
|
|
putvalu(valu, emit + (relo->or_addr - off), relo->or_type);
|
|
|
|
/*
|
|
* We must change the offset within the section of the value to be
|
|
* relocated to its offset in the new section. `Or_addr' must again be
|
|
* in the normal part, of course.
|
|
*/
|
|
relo->or_addr += relorig[sectindex].org_size;
|
|
}
|