148 lines
7.5 KiB
C
148 lines
7.5 KiB
C
/*
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* VideoCore IV assembler for the ACK
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* © 2013 David Given
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* This file is redistributable under the terms of the 3-clause BSD license.
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* See the file 'Copying' in the root of the distribution for the full text.
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*/
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/* Integer registers */
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0, GPR, 0, "r0",
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0, GPR, 1, "r1",
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0, GPR, 2, "r2",
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0, GPR, 3, "r3",
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0, GPR, 4, "r4",
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0, GPR, 5, "r5",
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0, GPR, 6, "r6",
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0, GPR, 7, "r7",
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0, GPR, 8, "r8",
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0, GPR, 9, "r9",
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0, GPR, 10, "r10",
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0, GPR, 11, "r11",
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0, GPR, 12, "r12",
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0, GPR, 13, "r13",
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0, GPR, 14, "r14",
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0, GPR, 15, "r15",
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0, GPR, 16, "r16",
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0, GPR, 17, "r17",
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0, GPR, 18, "r18",
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0, GPR, 19, "r19",
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0, GPR, 20, "r20",
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0, GPR, 21, "r21",
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0, GPR, 22, "r22",
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0, GPR, 23, "r23",
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0, GPR, 24, "r24",
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0, GPR, 24, "fp",
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0, GPR, 25, "r25",
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0, GPR, 25, "sp",
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0, GPR, 26, "r26",
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0, GPR, 26, "lr",
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0, GPR, 27, "r27",
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0, GPR, 28, "r28",
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0, GPR, 29, "r29",
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0, GPR, 30, "r30",
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0, GPR, 30, "sr",
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0, GPR, 31, "r31",
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0, GPR, 31, "pc",
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/* Condition codes */
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0, CC, 0, ".eq",
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0, CC, 1, ".ne",
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0, CC, 2, ".cs",
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0, CC, 2, ".lo",
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0, CC, 3, ".cc",
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0, CC, 3, ".hg",
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0, CC, 4, ".mi",
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0, CC, 5, ".pl",
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0, CC, 6, ".vs",
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0, CC, 7, ".vc",
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0, CC, 8, ".hi",
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0, CC, 9, ".ls",
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0, CC, 10, ".ge",
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0, CC, 11, ".lt",
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0, CC, 12, ".gt",
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0, CC, 13, ".le",
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0, CC, 15, ".f",
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/* Special instructions */
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0, OP, B16(00000000,00000001), "nop",
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0, OP, B16(00000000,00001010), "rti",
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0, OP_BRANCH, 0, "b",
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0, OP_BRANCHLINK, 0, "bl",
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0, OP_ADDCMPB, 0, "addcmpb",
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0, OP_ONELREG, B16(00000000,10000000), "tbb",
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0, OP_ONELREG, B16(00000000,10100000), "tbs",
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0, OP_ALU, B8(00000000), "mov",
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0, OP_ALU, B8(00000001), "cmn",
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0, OP_ALU, B8(00000010), "add",
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0, OP_ALU, B8(00000011), "bic",
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0, OP_ALU, B8(00000100), "mul",
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0, OP_ALU, B8(00000101), "eor",
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0, OP_ALU, B8(00000110), "sub",
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0, OP_ALU, B8(00000111), "and",
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0, OP_ALU, B8(00001000), "mvn",
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0, OP_ALU, B8(00001001), "ror",
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0, OP_ALU, B8(00001010), "cmp",
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0, OP_ALU, B8(00001011), "rsb",
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0, OP_ALU, B8(00001100), "btst",
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0, OP_ALU, B8(00001101), "or",
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0, OP_ALU, B8(00001110), "extu",
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0, OP_ALU, B8(00001111), "max",
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0, OP_ALU, B8(00010000), "bset",
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0, OP_ALU, B8(00010001), "min",
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0, OP_ALU, B8(00010010), "bclr",
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0, OP_ALU, B8(00010011), "adds2",
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0, OP_ALU, B8(00010100), "bchg",
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0, OP_ALU, B8(00010101), "adds4",
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0, OP_ALU, B8(00010110), "adds8",
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0, OP_ALU, B8(00010111), "adds16",
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0, OP_ALU, B8(00011000), "exts",
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0, OP_ALU, B8(00011001), "neg",
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0, OP_ALU, B8(00011010), "lsr",
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0, OP_ALU, B8(00011011), "clz",
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0, OP_ALU, B8(00011100), "lsl",
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0, OP_ALU, B8(00011101), "brev",
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0, OP_ALU, B8(00011110), "asr",
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0, OP_ALU, B8(00011111), "abs",
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0, OP_MISC, B16(11001000,00000000), "fadd",
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0, OP_MISC, B16(11001000,00100000), "fsub",
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0, OP_MISC, B16(11001000,01000000), "fmul",
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0, OP_MISC, B16(11001000,01100000), "fdiv",
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0, OP_MISC, B16(11001000,10000000), "fcmp",
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0, OP_MISC, B16(11001000,10100000), "fabs",
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0, OP_MISC, B16(11001000,11000000), "frsb",
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0, OP_MISC, B16(11001000,11100000), "fmax",
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0, OP_MISC, B16(11001001,00000000), "frcp",
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0, OP_MISC, B16(11001001,00100000), "frsqrt",
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0, OP_MISC, B16(11001001,01000000), "fnmul",
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0, OP_MISC, B16(11001001,01100000), "fmin",
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0, OP_MISC, B16(11001001,10000000), "fld1",
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0, OP_MISC, B16(11001001,10100000), "fld0",
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0, OP_MISC, B16(11001001,11000000), "log2",
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0, OP_MISC, B16(11001001,11100000), "exp2",
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0, OP_MISC, B16(11000101,11100000), "adds256",
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0, OP_MISCL, B16(11000100,10000000), "divs",
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0, OP_MISCL, B16(11000100,11100000), "divu",
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0, OP_STACK, B16(00000010,00000000), "push",
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0, OP_STACK, B16(00000010,10000000), "pop",
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0, OP_MEM, B8(00000000), "ld",
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0, OP_MEM, B8(00000001), "st",
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0, OP_MEM, B8(00000010), "ldh",
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0, OP_MEM, B8(00000011), "sth",
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0, OP_MEM, B8(00000100), "ldb",
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0, OP_MEM, B8(00000101), "stb",
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0, OP_MEM, B8(00000110), "ldhs",
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0, OP_MEM, B8(00000111), "sths",
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