82 lines
3.5 KiB
Text
82 lines
3.5 KiB
Text
.so init
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.nr H1 2
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.NH
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PROBLEMS
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.NH 2
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Maintain SPARC speed
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.PP
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If we want to generate SPARC code, we should try to generate efficient code
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as fast as possible. It would be quite embarrassing to find out that the
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same program would run faster on a Motorola 68020 than on a SPARC processor,
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when both operate at the same clock frequency.
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Looking at some code generated by Sun's C-compiler and optimizing assembler,
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we can spot a few remarkable characteristics of the generated SPARC code:
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.IP -
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There are almost no memory references
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.IP -
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Parameters to functions are passed through registers.
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.IP -
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Almost all delay slots\(dg
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.FS
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\(dg For details about delay slots see the SPARC Architecture Manual, chapter 4, pp. 42-48
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.FE
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are filled in by the assembler
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.LP
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If we want to generate efficient code, we should at least try to
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reduce the number of memory references and use registers wherever we can.
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Since EM is stack-oriented it references its stack for every operation so
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this will not be an easy task; a suitable solution will however be given in
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the next chapter.
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.NH 2
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Increase compilation speed
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.PP
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Because we will implement a code expander (fast backend) we should keep
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a close eye on efficiency; if we cannot beat regular compilers on producing
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efficient code we will try to beat them on fast code generation.
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The usual trick to achieve fast compilation is to pack the frontend,
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optimizer, code-generator and
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assembler all into a single large binary to reduce the overhead of
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reading and writing temporary files. Unfortunately, due to the
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SPARC instruction set, its relocation information is slightly bizarre
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and cannot be represented with the present primitives.
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This means that it will not be possible to generate the required output
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format directly from our backend.
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.PP
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There are three solutions here: generate assembler code, and let an
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existing assembler generate the required object (\fI.o\fR) files,
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create our own primitives than can handle the SPARC relocation format, or
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do not use any of the addressing modes that require the bizarre relocation.
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Because we have enough on our hands already we will
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let the existing assembler deal with generating object files.
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.NH 2
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Convert stack to register operations
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.PP
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As we wrote in the previous chapter, for RISC machines a code expander can
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produce almost as efficient code as a code generator. The fact that this is
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true for stack-oriented RISC processors is rather obvious. The problem we
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face, however, is that the SPARC processor is register, instead of
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stack oriented. In the next chapter we will give a suitable solution to
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convert most stack accesses to register accesses.
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.NH 2
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Miscellaneous
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.PP
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Besides performance and \fI.o\fR-compatibility there are some other
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peculiarities of the SPARC processor and Sun's C-compiler (henceforth
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simply called \fIcc\fR).
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.PP
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For some reason, the SPARC stack pointer requires alignment
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on 8 bytes, so it is impossible to push a 4-byte integer on the stack
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and then \*(Sisub 4, %sp\*(So\(dd.
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.FS
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\(dd For more information about SPARC assembler see the Sun-4 Assembly
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Language Reference Manual
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.FE
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This too will be discussed in the next chapter, where we will take a
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more in-depth look into this problem and also discuss a couple of
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possible solutions.
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.PP
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Another thing is that \fIcc\fR usually passes the first six parameters of a
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function-call through registers. To be \fI.o\fR-compatible we would have to
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pass the first six parameters of each function call through registers as well.
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Exactly why this is not feasible will also be discussed in the next chapter.
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.bp
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