167 lines
5.7 KiB
Groff
167 lines
5.7 KiB
Groff
.\" $Header$
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.TH Z8000_AS 6ACK
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.ad
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.SH NAME
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z8000_as \- assembler for Zilog z8000 (segmented version)
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.SH SYNOPSIS
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~em/lib/z8000/as [options] argument ...
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.SH DESCRIPTION
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This assembler is made with the general framework
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described in \fIuni_ass\fP(6). It is an assembler\-loader. Output is
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in \fIack.out\fP(5) format, but not relocatable.
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.SH SYNTAX
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.IP instructions
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Instruction mnemonics are implemented exactly as described in
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\fIZ8000 PLZ/ASM Assembly Language Programming Manual\fP and
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\fIAmZ8001/2 Processor Instruction Set\fP.
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.IP registers
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The z8000 has sixteen 16-bit general purpose registers specified
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as R0 through R15. All sixteen registers can be used as accumulators.
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In addition to this, fifteen of the sixteen registers may be used
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in addressing mode calculations as either indirect, index or
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base-address registers. Because the instruction format encoding
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uses the value zero to differentiate between various addressing
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modes, register R0 (or the register pair RR0) cannot be used as an
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indirect, index or base-address register.
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It is also possible to address registers as groups of 8, 32 or 64 bits.
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These registers are specified as follows.
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.nf
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.ta 8n 16n 24n 32n 40n 48n
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- RH0, RL0, RH1, RL1, ..., RH7, RL7 for 8-bit regis-
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ters. (\fIH\fP stands for high-order byte, and \fIL\fP stands
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for low-order byte within a word register). These
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registers overlap 16-bit registers R0 through R7.
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- RR0, RR2, ..., RR14 for 32-bit register pairs.
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- RQ0, RQ4, RQ8 and RQ12 for 64-bit register quadruples.
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.fi
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Besides register pair RR14 is used as stackpointer.
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.IP "addressing modes"
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.nf
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.ta 8n 16n 24n 32n 40n 48n
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syntax meaning (name-mnemonic)
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$expr the value of expr is the operand.
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(immediate-IM)
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reg contents of register reg is operand. Any
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register as described above is allowed.
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(register-R)
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*reg32 contents of register pair reg32 is add-
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ress of operand. Any register pair can
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be used except RR0.
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(indirect register-IR)
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expr expr is address of operand.
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(direct address-DA)
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expr(reg16) value of expr + contents of word regis-
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ter reg16 yields address of operand.
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Any word register can be used except R0.
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(indexed address-X)
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expr expr is address of operand. This mode
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is implied by its instruction. It is
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only used by CALR, DJNZ, JR, LDAR and
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LDR and is the only mode available to
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these instructions. In fact this mode
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differs not from the mode DA.
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(relative address-RA)
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reg32($expr) contents of register pair reg32 + value
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of expr yields address of operand. Any
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register pair can be used except RR0.
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(based address-BA)
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reg32(reg16) contents of register pair reg32 + con-
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tents of word register reg16 yields
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address of operand. Any register pair/
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word register can be used except RR0/R0.
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(based indexed address-BX)
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.fi
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.IP "segmented addresses"
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Segmented addresses require 23 bits, 7 bits for the segment number
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and 16 bits for the offset within a segment.
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So segment 0 contains addresses 0-FFFF, segment 1 contains addresses
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10000-1FFFF, and so on.
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.br
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Assembler syntax of addresses and immediate data is as described above
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(modes IM, DA and X).
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Thus the assembler treats e.g. address 2BC0F as an address in segment 2
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with offset BC0F within the segment.
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There is also an explicit way to express this using the, more unusual,
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syntax <<segment>>offset.
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.br
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There are two internal representations of segmented addresses
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depending on the size of the offset. If the offset fits into 8 bits
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the address is stored in one word (the low-order byte containing
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the offset, bits 8 to 14 containing the segment number and
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bit 15 containing a zero) otherwise the address is stored in two
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words (the lower word containing the offset, the upper word as
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before but bit 15 containing 1 indicating that the offset is in
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the next word).
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This is important for instructions which has an operand of mode DA
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or X.
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.IP "extended branches"
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When the target address in a relative jump/call (JR/CALR)
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does not fit into the instruction format, the assembler generates
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a corresponding `normal' jump/call (JP/CALL).
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.SH EXAMPLE
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An example of z8000 assembly code.
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.nf
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.ta 8n 16n 24n 32n 40n 48n
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! This z8000 assembly routine converts a positive number
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!(in R1) to a string representing the number and puts this
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!string into a buffer (R3 contains the starting address of
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!this buffer. The base is in R4 determining %x, %d or %o.
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.sect .text
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convert:
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exts RR0 !sign-extend R1
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div RR0, R4 !divide by the base
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test R1 !R1 contains the quotient
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jr EQ, 5f
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!if quotient is 0 convert is ready
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!else push remainder onto the stack
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push *RR14, R0
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calr convert !and again...
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pop R0, *RR14
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5: add R0, $060 !add `0'
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cp R0, $071 !compare to `9'
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jr LE, 8f
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add R0, $7 !in case of %x `A'-`F'
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8: ldb 0(R3), RL0 !put character into buffer
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inc R3
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ret
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.fi
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.SH "SEE ALSO"
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uni_ass(6),
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ack(1),
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ack.out(5),
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.br
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Z8000 PLZ/ASM Assembly Language Programming Manual, april 1979.
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.br
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AmZ8001/2 Processor Instruction Set, 1979.
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.SH BUGS
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You cannot use (reg16) instead of 0(reg16).
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.br
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Condition codes \fIZ\fP (meaning zero), \fIC\fP (meaning carry) and <nothing>
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(meaning always false) are not implemented.
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The first two because they also represent flags and the third one
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because it's useless.
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So for \fIZ\fP/\fIC\fP use \fIEQ\fP/\fIULT\fP.
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.br
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The z8000 assembly instruction set as described in the book
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\fIAmZ8001/2 Processor Instruction Set\fP differs from the one
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described in the manual \fIZ8000 PLZ/ASM Assembly Language Programming
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Manual\fP in that the book includes CLRL, LDL (format F5.1) and
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PUSHL (format F5.1) which all in fact do not (!) work.
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.br
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On the other side the book excludes SIN, SIND, SINDR, SINI, SINIR,
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SOUT, SOUTD, SOTDR, SOUTI and SOTIR.
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Whether these instructions do work as described in the manual has not
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been tested yet.
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