501 lines
12 KiB
C
501 lines
12 KiB
C
/*
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* VideoCore IV assembler for the ACK
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* © 2013 David Given
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* This file is redistributable under the terms of the 3-clause BSD license.
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* See the file 'Copying' in the root of the distribution for the full text.
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*/
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#include <stdint.h>
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#define maskx(v, x) (v & ((1<<(x))-1))
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static void toobig(void)
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{
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serror("offset too big to encode into instruction");
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}
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/* Assemble an ALU instruction where rb is a register. */
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void alu_instr_reg(quad op, int cc, int rd, int ra, int rb)
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{
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/* Can we use short form? */
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if ((cc == ALWAYS) && (ra == rd) && (ra < 0x10) && (rb < 0x10))
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{
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emit2(B16(01000000,00000000) | (op<<8) | (rb<<4) | (rd<<0));
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return;
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}
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/* Long form, then. */
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emit2(B16(11000000,00000000) | (op<<5) | (rd<<0));
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emit2(B16(00000000,00000000) | (ra<<11) | (cc<<7) | (rb<<0));
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}
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/* Assemble an ALU instruction where rb is a literal. */
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void alu_instr_lit(quad op, int cc, int rd, int ra, long value)
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{
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/* 16 bit short form? */
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if ((cc == ALWAYS) && !(op & 1) && (value >= 0) && (value <= 0x1f) &&
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(ra == rd) && (ra < 0x10))
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{
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emit2(B16(01100000,00000000) | (op<<8) | (value<<4) | (rd<<0));
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return;
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}
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/* 32 bit medium form? */
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if ((value >= 0) && (value <= 0x1f))
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{
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emit2(B16(11000000,00000000) | (op<<5) | (rd<<0));
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emit2(B16(00000000,01000000) | (ra<<11) | (cc<<7) | (value<<0));
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return;
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}
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/* Long form, then. */
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if (cc != ALWAYS)
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serror("cannot use condition codes with ALU literals this big");
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/* add is special. */
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if (op == B8(00000010))
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emit2(B16(11101100,00000000) | (ra<<5) | (rd<<0));
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else
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{
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if (ra != rd)
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serror("can only use 2op form of ALU instructions with literals this big");
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emit2(B16(11101000,00000000) | (op<<5) | (rd<<0));
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}
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emit4(value);
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}
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/* Miscellaneous instructions with three registers and a cc. */
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void misc_instr_reg(quad op, int cc, int rd, int ra, int rb)
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{
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emit2(op | (rd<<0));
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emit2(B16(00000000,00000000) | (ra<<11) | (cc<<7) | (rb<<0));
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}
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/* Miscellaneous instructions with two registers, a literal, and a cc. */
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void misc_instr_lit(quad op, int cc, int rd, int ra, quad value)
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{
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if (value < 0x1f)
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serror("only constants from 0..31 can be used here");
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emit2(op | (rd<<0));
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emit2(B16(00000000,01000000) | (ra<<11) | (cc<<7) | (value<<0));
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}
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/* Assemble a branch instruction. This may be a near branch into this
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* object file, or a far branch which requires a fixup. */
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void branch_instr(int bl, int cc, struct expr_t* expr)
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{
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quad pc = DOTVAL;
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quad type = expr->typ & S_TYP;
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int d;
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/* Sanity checking. */
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if (bl && (cc != ALWAYS))
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serror("can't use condition codes with bl");
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if (type == S_ABS)
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serror("can't use absolute addresses here");
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/* The VC4 branch instructions express distance in 2-byte
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* words. */
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d = (int32_t)expr->val - (int32_t)pc;
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if ((pass == 2) && (d > 0) && !(expr->typ & S_DOT))
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d -= DOTGAIN;
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d /= 2;
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/* If this is a reference to code within this section, and it's
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* close enough to the program counter, we can use a short-
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* form instruction. */
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if (small(!bl && (type == DOTTYP) && fitx(d, 7), 2))
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{
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emit2(B16(00011000,00000000) | (cc<<7) | (d&0x7f));
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return;
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}
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/* Absolute addresses and references to other sections
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* need the full 32 bits. */
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newrelo(expr->typ, RELOVC4|RELPC);
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if (bl)
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{
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quad v, hiv, lov;
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if (!fitx(d, 27))
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toobig();
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v = maskx(d, 27);
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hiv = v >> 23;
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lov = v & 0x007fffff;
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emit2(B16(10010000,10000000) | (lov>>16) | (hiv<<8));
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emit2(B16(00000000,00000000) | (lov&0xffff));
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}
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else
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{
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quad v;
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if (!fitx(d, 23))
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toobig();
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v = maskx(d, 23);
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emit2(B16(10010000,00000000) | (cc<<8) | (v>>16));
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emit2(B16(00000000,00000000) | (v&0xffff));
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}
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}
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/* Push/pop. */
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void stack_instr(quad opcode, int loreg, int hireg, int extrareg)
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{
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int b;
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int m;
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switch (loreg)
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{
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case 0: b = 0; break;
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case 6: b = 1; break;
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case 16: b = 2; break;
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case 24: b = 3; break;
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case 26: /* lr */
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extrareg = 26;
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hireg = loreg = -1;
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break;
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case 31: /* pc */
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extrareg = 31;
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hireg = loreg = -1;
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break;
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default:
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serror("base register for push or pop may be only r0, r6, r16, r24, lr or pc");
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}
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if (opcode & 0x0080)
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{
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/* Push */
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if (extrareg == 31)
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serror("cannot push pc");
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}
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else
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{
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/* Pop */
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if (extrareg == 26)
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serror("cannot pop lr");
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}
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if (hireg < loreg)
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serror("invalid register range");
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if (hireg == -1)
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{
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b = 3;
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m = 15;
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}
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else
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m = hireg - loreg;
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emit2(opcode | (b<<5) | (m<<0) | ((extrareg != -1) ? 0x0100 : 0));
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}
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/* Memory operations where the offset is a fixed value (including zero). */
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void mem_instr(quad opcode, int cc, int rd, long offset, int rs)
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{
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quad uoffset = (quad) offset;
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int multiple4 = !(offset & 3);
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int intonly = ((opcode & B8(00000110)) == 0);
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/* If no CC, there are some special forms we can use. */
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if (cc == ALWAYS)
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{
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/* Very short form, special for stack offsets. */
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if (intonly && (rs == 25) && multiple4 && fitx(offset, 7) && (rd < 0x10))
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{
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quad o = maskx(offset, 7) / 4;
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emit2(B16(00000100,00000000) | (opcode<<9) | (o<<4) | (rd<<0));
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return;
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}
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/* Slightly longer form for directly dereferencing via a register. */
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if ((rs < 0x10) && (rd < 0x10) && (offset == 0))
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{
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emit2(B16(00001000,00000000) | (opcode<<8) | (rs<<4) | (rd<<0));
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return;
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}
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/* Integer only, but a limited offset. */
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if (intonly && (uoffset <= 0x3f) && (rs < 0x10) && (rd < 0x10))
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{
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quad o = uoffset / 4;
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emit2(B16(00100000,00000000) | (opcode<<12) | (o<<8) |
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(rs<<4) | (rd<<0));
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return;
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}
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/* Certain registers support 16-bit offsets. */
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if (fitx(offset, 16))
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{
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switch (rs)
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{
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case 0: opcode = B16(10101011,00000000) | (opcode<<5); goto specialreg;
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case 24: opcode = B16(10101000,00000000) | (opcode<<5); goto specialreg;
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case 25: opcode = B16(10101001,00000000) | (opcode<<5); goto specialreg;
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case 31: opcode = B16(10101010,00000000) | (opcode<<5); goto specialreg;
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default: break;
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specialreg:
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{
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quad o = maskx(offset, 16);
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emit2(opcode | (rd<<0));
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emit2(o);
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return;
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}
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}
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}
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/* 12-bit displacements. */
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if (fitx(offset, 12))
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{
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quad looffset = maskx(offset, 11);
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quad hioffset = (offset >> 11) & 1;
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emit2(B16(10100010,00000000) | (opcode<<5) | (rd<<0) | (hioffset<<8));
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emit2(B16(00000000,00000000) | (rs<<11) | (looffset<<0));
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return;
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}
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/* Everything else uses Very Long Form. */
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if (!fitx(offset, 27))
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serror("offset will not fit into load/store instruction");
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if (rs == 31)
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opcode = B16(11100111,00000000) | (opcode<<5);
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else
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opcode = B16(11100110,00000000) | (opcode<<5);
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emit2(opcode | (rd<<0));
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emit4((rs<<27) | maskx(offset, 27));
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return;
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}
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/* Now we're on to load/store instructions with ccs. */
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if (uoffset <= 0x1f)
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{
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emit2(B16(10100000,00000000) | (opcode<<5) | (rd<<0));
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emit2(B16(00000000,01000000) | (rs<<11) | (cc<<7) | (uoffset<<0));
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return;
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}
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/* No encoding for this instruction. */
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serror("invalid load/store instruction");
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}
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/* Memory operations where the destination address is a sum of two
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* registers. */
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void mem_offset_instr(quad opcode, int cc, int rd, int ra, int rb)
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{
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emit2(B16(10100000,00000000) | (opcode<<5) | (rd<<0));
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emit2(B16(00000000,00000000) | (ra<<11) | (cc<<7) | (rb<<0));
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}
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/* Memory operations with postincrement. */
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void mem_postincr_instr(quad opcode, int cc, int rd, int rs)
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{
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emit2(B16(10100101,00000000) | (opcode<<5) | (rd<<0));
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emit2(B16(00000000,00000000) | (rs<<11) | (cc<<7));
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}
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/* Memory operations where the destination is an address literal. */
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void mem_address_instr(quad opcode, int rd, struct expr_t* expr)
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{
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static const char sizes[] = {4, 4, 2, 2, 1, 1, 2, 2};
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int size = sizes[opcode];
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quad type = expr->typ & S_TYP;
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int d, scaledd;
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/* Sanity checking. */
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if (type == S_ABS)
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serror("can't use absolute addresses here");
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d = expr->val - DOTVAL;
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if ((pass == 2) && (d > 0) && !(expr->typ & S_DOT))
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d -= DOTGAIN;
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scaledd = d/size;
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/* If this is a reference to an address within this section, and
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* it's close enough to the program counter, we can use a
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* shorter instruction. */
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if (small((type==DOTTYP) && fitx(scaledd, 16), 2))
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{
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emit2(B16(10101010,00000000) | (opcode<<5) | (rd<<0));
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emit2(scaledd);
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return;
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}
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/* Otherwise we need the full 48 bits. */
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newrelo(expr->typ, RELOVC4|RELPC);
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/* VC4 relocations store the PC-relative delta into the
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* destination section in the instruction data. The linker will
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* massage this, and scale it appropriately. */
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if (!fitx(d, 27))
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toobig();
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emit2(B16(11100111,00000000) | (opcode<<5) | (rd<<0));
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emit4((31<<27) | maskx(d, 27));
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}
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/* Common code for handling addcmp: merge in as much of expr as will fit to
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* the second pair of the addcmp opcode. */
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static void branch_addcmp_common(quad opcode, int bits, struct expr_t* expr)
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{
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quad type = expr->typ & S_TYP;
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int d;
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if ((pass>0) && (type != DOTTYP))
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serror("can't use this type of branch to jump outside the section");
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/* The VC4 branch instructions express distance in 2-byte
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* words. */
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d = (expr->val - DOTVAL-2 + 4);
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if ((pass == 2) && (d > 0) && !(expr->typ & S_DOT))
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d -= DOTGAIN;
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d /= 2;
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if ((pass == 2) && !fitx(d, bits))
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serror("target of branch is too far away");
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emit2(opcode | maskx(d, bits));
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}
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void branch_addcmp_reg_reg_instr(int cc, int rd, int ra, int rs, struct expr_t* expr)
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{
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if ((rd >= 0x10) || (ra >= 0x10) || (rs >= 0x10))
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serror("can only use r0-r15 in this instruction");
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emit2(B16(10000000,00000000) | (cc<<8) | (ra<<4) | (rd<<0));
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branch_addcmp_common(B16(00000000,00000000) | (rs<<10), 10, expr);
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}
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void branch_addcmp_lit_reg_instr(int cc, int rd, long va, int rs, struct expr_t* expr)
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{
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if ((rd >= 0x10) || (rs >= 0x10))
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serror("can only use r0-r15 in this instruction");
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if (!fitx(va, 4))
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serror("value too big to encode into instruction");
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va = maskx(va, 4);
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emit2(B16(10000000,00000000) | (cc<<8) | (va<<4) | (rd<<0));
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branch_addcmp_common(B16(01000000,00000000) | (rs<<10), 10, expr);
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}
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void branch_addcmp_reg_lit_instr(int cc, int rd, int ra, long vs, struct expr_t* expr)
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{
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if ((rd >= 0x10) || (ra >= 0x10))
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serror("can only use r0-r15 in this instruction");
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if (!fitx(vs, 6))
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serror("value too big to encode into instruction");
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vs = maskx(vs, 6);
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emit2(B16(10000000,00000000) | (cc<<8) | (ra<<4) | (rd<<0));
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branch_addcmp_common(B16(10000000,00000000) | (vs<<8), 8, expr);
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}
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void branch_addcmp_lit_lit_instr(int cc, int rd, long va, long vs, struct expr_t* expr)
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{
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if (rd >= 0x10)
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serror("can only use r0-r15 in this instruction");
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if (!fitx(va, 4) || !fitx(vs, 6))
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serror("value too big to encode into instruction");
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va = maskx(va, 4);
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vs = maskx(vs, 6);
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emit2(B16(10000000,00000000) | (cc<<8) | (va<<4) | (rd<<0));
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branch_addcmp_common(B16(11000000,00000000) | (vs<<8), 8, expr);
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}
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/* lea, where the source is relative to the stack. */
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void lea_stack_instr(int rd, long va, int rs)
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{
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if (rs != 25)
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serror("source register must be sp");
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va /= 4;
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if (!fitx(va, 6))
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serror("offset too big to encode in instruction");
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va = maskx(va, 6);
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emit2(B16(00010000,00000000) | (rd<<0) | (va<<5));
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}
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/* lea, where the source is an address. */
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void lea_address_instr(int rd, struct expr_t* expr)
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{
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quad pc = DOTVAL;
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quad type = expr->typ & S_TYP;
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int d = expr->val - pc;
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if ((pass == 2) && (d > 0) && !(expr->typ & S_DOT))
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d -= DOTGAIN;
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if (type == S_ABS)
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serror("can't use absolute addresses here");
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newrelo(expr->typ, RELOVC4|RELPC);
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/* VC4 relocations store the PC-relative delta into the
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* destination section in the instruction data. The linker will
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* massage this, and scale it appropriately. */
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emit2(B16(11100101,00000000) | (rd<<0));
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emit4(expr->val - pc);
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}
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/* Floating point conversion opcodes (ftrunc, floor, flts, fltu). */
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void fltcnv_instr(quad opcode, int cc, int rd, int ra, quad shift)
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{
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fitx(shift, 6);
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emit2(opcode | (rd<<0));
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emit2(B16(00000000,01000000) | (ra<<11) | (cc<<7) | shift);
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}
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