138 lines
3.9 KiB
Groff
138 lines
3.9 KiB
Groff
.\" $Header$
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.TH PDP_AS 1
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.ad
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.SH NAME
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pdp_as \- assembler for PDP 11
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.SH SYNOPSIS
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/usr/em/lib/pdp_as [options] argument ...
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.SH DESCRIPTION
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This assembler is made with the general framework
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described in \fIuni_ass\fP(6).
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.SH SYNTAX
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.IP registers
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The pdp11 has seven general registers, numbered r0 through r7.
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Of these, r6 is the stack pointer and can also be referenced to by \fIsp\fP,
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r7 is the program counter and has \fIpc\fP as synonym. There are also six
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floating-point registers fr0 through fr5, but the names r0 through r5 can
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also be used. From the context will be derived what kind of register is meant.
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.IP "addressing modes"
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.nf
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.ta 8n 16n 24n 32n 40n 48n
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syntax meaning (name)
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reg contents of register reg is operand.
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(register)
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(reg) contents of reg is address of operand.
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(register deferred)
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(reg)+ as (reg), but after the operand is fetched
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the contents of reg is incremented by the
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size of the operand. (auto-increment)
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*(reg)+ contents of reg points to address of the operand.
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after the operand is fetched, reg is incremented
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by two. (auto-increment deferred)
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-(reg) as (reg), but before the operand is fetched
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the contents of reg is decremented by the
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size of the operand. (auto-decrement)
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*-(reg) before the operand is fetched, reg is decremented
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by two. then the contents of reg points to the
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address of the operand. (auto-decrement deferred)
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expr(reg) value of expr + contents of reg yields address
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of operand. (index)
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*expr(reg) value of expr + contents of reg yields pointer
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to address of operand. (index deferred)
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$expr the value of expr is the operand. (immediate)
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*$expr the value of expr is the address of the operand.
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(absolute)
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expr expr is address of operand. (relative)
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*expr expr points to the address of the operand.
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(relative deferred)
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.fi
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.IP "condition code instructions"
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Two or more of the "clear" instructions (clc, cln, clv, clz), or
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two or more of the "set" instructions (sec, sen, sev, sez) may be
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or-ed together with `|' to yield a instruction that clears or sets two or more
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of the condition-bits. Scc and ccc are not predefined.
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.IP "extended branches"
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The assembler recognizes conditional branches with a "j" substituted for
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the "b". When the target is too remote for a simple branch, a converse branch
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over a jmp to the target is generated. Likewise jbr assembles into either br
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or jmp.
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.IP "floating-point instructions"
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The names of several floating-point instructions differ from the names
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in the handbook mentioned below. Synonyms ending in "d" for instructions ending
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in "f" are not recognized. Some instructions have different names; the mapping
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is as below.
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.nf
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.ta 8n 16n 24n 32n 40n 48n
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handbook pdp_as
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ldcif, ldclf,
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ldcid, ldcld movif
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stcfi, stcfl,
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stcdi, stcdl movfi
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ldcdf, ldcfd movof
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stcdf, stcfd movfo
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ldexp movie
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stexp movei
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ldd, ldf movf
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std, stf movf
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.fi
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The movf instruction assembles into stf, when the first operand is one of the
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first three floating-point registers, otherwise it assembles into ldf.
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.IP sys
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This instruction is synonymous with trap.
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.SH EXAMPLE
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An example of pdp11 assembly code.
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.nf
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.ta 8n 16n 24n 32n 40n 48n
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!this is the routine that reads numbers into r0
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!the number is terminated by any non digit
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!the non digit is left in r1
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innum: clr r3 !r3 will accumulate the number
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inloop: jsr pc,_getchar !read a character into r0
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cmp r0,$0121 !is it a Q?
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jeq quit
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cmp r0,$48 !is the character a digit?
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jlt indone !digits 0-9 have codes 060-071 octal
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cmp r0,$56
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jgt indone
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mul $10,r3 !r3 = 10 * r3
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sub $48,r3 !convert ascii code to numerical value
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add r0,r3 !r3 = old sum * 10 + new digi
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jbr inloop
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indone: mov r0,r1 !put the first non digit into r1
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mov r3,r0 !put the number read into r0
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rts pc !return to caller
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.fi
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.SH "SEE ALSO"
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uni_ass(6),
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ack(1),
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.br
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PDP11/60 processor handbook, Digital Equipment Corporation, 1977
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.SH BUGS
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You cannot use *reg in place of (reg). Likewise *(reg) is not understood as
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*0(reg).
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