5aa2ac2246
Also make a few changes to basic mnemonics. Fix typo in name of the basic "creqv". Add the basic "addc" and relatives, because it would be odd to have the extended "subc" without "addc". Fix the basic "rldicl", "rldicr", "rldic", "rldimi" to correctly encode the 6-bit MB field. Fix "slw" and relatives to correctly swap their RA and RS operands. Add many, but not all, of the extended mnemonics from IBM's Power ISA Version 2.06 Book I Appendix E. (I used 2.06, published 2009, just because I already had the PDF of it.) This commit includes mnemonics for branching, subtraction, traps, bit rotation, and a few others, like "mflr" and "nop". The assembler now understands branches like `beq cr7, label` and bit shifts like `slwi r7, r7, 2`. These encode the same machine instructions as the basic "bc" and "rlwinm". Some operands to basic names become optional. The assembler no longer requires the level in "sc" or the branch hint in "bcctr" and "bclr"; they default to zero. Some extended names take an optional branch hint or condition register. Some extended names are still missing. I don't provide names with static branch prediction, like "beq+" or "bge-", because the assembler parses '+' and '-' as operators, not as part of an instruction name. I also don't provide some names that 2.06 has for moving to or from the condition register or some special purpose registers, names like "mtcr" or "mfuamr". This commit also deletes some unused tokens and one unused yacc rule.
40 lines
832 B
C
40 lines
832 B
C
/*
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* $Source$
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* $State$
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*/
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#define THREE_PASS /* branch and offset optimization */
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#define BYTES_REVERSED /* high order byte has lowest address */
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#define WORDS_REVERSED /* high order word has lowest address */
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#define LISTING /* enable listing facilities */
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#define RELOCATION /* generate relocatable code */
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#define DEBUG 0
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#undef valu_t
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#define valu_t long
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#undef ADDR_T
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#define ADDR_T long
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#undef word_t
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#define word_t long
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typedef uint32_t quad;
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#undef ALIGNWORD
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#define ALIGNWORD 4
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#undef ALIGNSECT
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#define ALIGNSECT 4
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#undef VALWIDTH
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#define VALWIDTH 8
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#define FIXUPFLAGS (RELBR | RELWR)
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/* 6-bit mb (mask begin) or me (mask end) field */
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#define MB6(v) (((v) & 0x1F)<<6 | ((v) & 0x20)>>0)
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/* 6-bit sh (shift) field */
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#define SH6(v) (((v) & 0x1F)<<11 | ((v) & 0x20)>>4)
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