720 lines
21 KiB
Plaintext
720 lines
21 KiB
Plaintext
REGISTERS
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/* Registers are allocated top down; the order here is odd in order to make
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* sure that non-volatile registers get allocated from r31 (or f31) down.
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*
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* Attributes ending in an exclamation mark must match exactly when copying
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* a register into another register (e.g. for eviction).
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*/
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r12 bytes4! int! volatile;
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r11 bytes4! int! volatile;
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r10 bytes4! int! volatile;
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r9 bytes4! int! volatile;
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r8 bytes4! int! volatile;
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r7 bytes4! int! volatile;
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r6 bytes4! int! volatile;
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r5 bytes4! int! volatile;
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r4 bytes4! int! volatile;
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r3 bytes4! int! volatile ret;
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r31 bytes4! int!;
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r30 bytes4! int!;
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r29 bytes4! int!;
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r28 bytes4! int!;
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r27 bytes4! int!;
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r26 bytes4! int!;
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r25 bytes4! int!;
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r24 bytes4! int!;
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r23 bytes4! int!;
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r22 bytes4! int!;
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r21 bytes4! int!;
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r20 bytes4! int!;
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r19 bytes4! int!;
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r18 bytes4! int!;
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r17 bytes4! int!;
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r16 bytes4! int!;
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r15 bytes4! int!;
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r14 bytes4! int!;
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r13 bytes4! int!;
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r11r12 named("r11", "r12") aliases(r11, r12) bytes8! long! volatile;
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r9r10 named("r9", "r10") aliases(r9, r10) bytes8! long! volatile;
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r7r8 named("r7", "r8") aliases(r7, r8) bytes8! long! volatile;
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r5r6 named("r5", "r6") aliases(r6, r6) bytes8! long! volatile;
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r3r4 named("r3", "r4") aliases(r3, r4) bytes8! long! volatile pret;
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r29r30 named("r29", "r30") aliases(r29, r30) bytes8! long!;
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r27r28 named("r27", "r28") aliases(r27, r28) bytes8! long!;
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r25r26 named("r25", "r26") aliases(r25, r26) bytes8! long!;
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r23r24 named("r23", "r24") aliases(r23, r24) bytes8! long!;
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r21r22 named("r21", "r22") aliases(r21, r22) bytes8! long!;
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r19r20 named("r19", "r20") aliases(r19, r20) bytes8! long!;
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r17r18 named("r17", "r18") aliases(r17, r18) bytes8! long!;
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r15r16 named("r15", "r16") aliases(r15, r16) bytes8! long!;
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r13r14 named("r13", "r14") aliases(r13, r14) bytes8! long!;
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f14 bytes4! float! volatile;
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f13 bytes4! float! volatile;
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f12 bytes4! float! volatile;
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f11 bytes4! float! volatile;
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f10 bytes4! float! volatile;
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f9 bytes4! float! volatile;
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f8 bytes4! float! volatile;
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f7 bytes4! float! volatile;
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f6 bytes4! float! volatile;
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f5 bytes4! float! volatile;
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f4 bytes4! float! volatile;
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f3 bytes4! float! volatile fret;
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f2 bytes4! float! volatile;
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f1 bytes4! float! volatile;
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f0 bytes4! float! volatile;
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f31 bytes4! float!;
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f30 bytes4! float!;
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f29 bytes4! float!;
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f28 bytes4! float!;
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f27 bytes4! float!;
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f26 bytes4! float!;
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f25 bytes4! float!;
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f24 bytes4! float!;
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f23 bytes4! float!;
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f22 bytes4! float!;
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f21 bytes4! float!;
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f20 bytes4! float!;
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f19 bytes4! float!;
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f18 bytes4! float!;
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f17 bytes4! float!;
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f16 bytes4! float!;
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f15 bytes4! float!;
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d14 named("f14") aliases(f14) bytes8! double! volatile;
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d13 named("f13") aliases(f13) bytes8! double! volatile;
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d12 named("f12") aliases(f12) bytes8! double! volatile;
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d11 named("f11") aliases(f11) bytes8! double! volatile;
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d10 named("f10") aliases(f10) bytes8! double! volatile;
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d9 named("f9") aliases(f9) bytes8! double! volatile;
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d8 named("f8") aliases(f8) bytes8! double! volatile;
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d7 named("f7") aliases(f7) bytes8! double! volatile;
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d6 named("f6") aliases(f6) bytes8! double! volatile;
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d5 named("f5") aliases(f5) bytes8! double! volatile;
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d4 named("f4") aliases(f4) bytes8! double! volatile;
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d3 named("f3") aliases(f3) bytes8! double! volatile dret;
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d2 named("f2") aliases(f2) bytes8! double! volatile;
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d1 named("f1") aliases(f1) bytes8! double! volatile;
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d0 named("f0") aliases(f0) bytes8! double! volatile;
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d31 named("f31") aliases(f31) bytes8! double!;
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d30 named("f30") aliases(f30) bytes8! double!;
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d29 named("f29") aliases(f29) bytes8! double!;
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d28 named("f28") aliases(f28) bytes8! double!;
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d27 named("f27") aliases(f27) bytes8! double!;
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d26 named("f26") aliases(f26) bytes8! double!;
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d25 named("f25") aliases(f25) bytes8! double!;
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d24 named("f24") aliases(f24) bytes8! double!;
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d23 named("f23") aliases(f23) bytes8! double!;
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d22 named("f22") aliases(f22) bytes8! double!;
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d21 named("f21") aliases(f21) bytes8! double!;
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d20 named("f20") aliases(f20) bytes8! double!;
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d19 named("f19") aliases(f19) bytes8! double!;
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d18 named("f18") aliases(f18) bytes8! double!;
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d17 named("f17") aliases(f17) bytes8! double!;
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d16 named("f16") aliases(f16) bytes8! double!;
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d15 named("f15") aliases(f15) bytes8! double!;
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cr0 cr!;
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DECLARATIONS
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cr;
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ubyteX; /* bottom 8 bits valid, the rest undefined */
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ubyte0; /* bottom 8 bits valid, the rest 0 */
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ushortX; /* bottom 16 bits valid, the rest undefined */
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ushort0; /* bottom 16 bits valid, the rest 0 */
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address fragment;
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PATTERNS
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/* Special */
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PAIR(BLOCK.I, BLOCK.I);
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/* Miscellaneous special things */
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PUSH.I(in:(int)reg)
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emit "stwu %in, -4(sp)"
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cost 4;
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PUSH.L(in:(long)reg)
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emit "stwu %in.0, -4(sp)"
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emit "stwu %in.1, -4(sp)"
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cost 8;
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PUSH.D(in:(double)reg)
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emit "stfdu %in, -8(sp)"
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cost 4;
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out:(int)reg = POP.I
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emit "lwz %out, 0(sp)"
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emit "addi sp, sp, 4"
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cost 8;
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out:(long)reg = POP.L
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emit "lwz %out.0, 4(sp)"
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emit "lwz %out.1, 0(sp)"
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emit "addi sp, sp, 8"
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cost 12;
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out:(float)reg = POP.F
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emit "lfs %out, 0(sp)"
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emit "addi sp, sp, 4"
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cost 8;
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SETRET.I(in:(ret)reg)
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emit "! setret4"
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cost 1;
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SETRET.L(in:(pret)reg)
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emit "! setret8"
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cost 1;
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STACKADJUST.I(delta:CONST.I)
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when signed_constant(%delta, 16)
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emit "addi sp, sp, $delta"
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cost 4;
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STACKADJUST.I(in:(int)reg)
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emit "add sp, sp, %in"
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cost 4;
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out:(int)reg = GETFP.I
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emit "mr %out, fp"
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cost 4;
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out:(int)reg = FPTOARGS.I(GETFP.I)
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emit "addi %out, fp, 8"
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cost 4;
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out:(int)reg = FPTOARGS.I(in:(int)reg)
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emit "addi %out, %in, 8"
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cost 4;
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out:(int)reg = GETSP.I
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emit "mr %out, sp"
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cost 4;
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SETSP.I(in:(int)reg)
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emit "mr sp, %in"
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cost 4;
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out:(int)reg = COPYF.I(in:(float)reg)
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emit "stfsu %in, -4(sp)"
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emit "lwz %out, 0(sp)"
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emit "addi sp, sp, 4"
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cost 12;
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out:(double)reg = COPYL.D(in:(long)reg)
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emit "stwu %in.0, -4(sp)"
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emit "stwu %in.1, -4(sp)"
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emit "lfd %out, 0(sp)"
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emit "addi sp, sp, 8"
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cost 16;
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/* Memory operations */
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/* Stores */
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STORE.L(addr:address, value:(long)reg)
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emit "stw %value.0, 4+%addr"
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emit "stw %value.1, 0+%addr"
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cost 4;
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STORE.I(addr:address, value:(int)reg)
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emit "stw %value, %addr"
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cost 4;
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STOREH.I(addr:address, value:(int)ushortX)
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emit "sth %value, %addr"
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cost 4;
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STOREH.I(ADD.I(left:(int)reg, right:(int)reg), value:(int)ushortX)
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emit "sthx %value, %left, %right"
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cost 4;
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STOREB.I(addr:address, value:(int)ushortX)
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emit "sth %value, %addr"
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cost 4;
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STOREB.I(addr:address, value:(int)ubyteX)
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emit "stb %value, %addr"
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cost 4;
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STOREB.I(ADD.I(left:(int)reg, right:(int)reg), value:(int)ubyteX)
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emit "stbx %value, %left, %right"
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cost 4;
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/* Loads */
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out:(int)reg = LOAD.I(addr:address)
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emit "lwz %out, %addr"
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cost 4;
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out:(long)reg = LOAD.L(addr:address)
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emit "lwz %out.0, 4+%addr"
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emit "lwz %out.1, 0+%addr"
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cost 8;
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out:(double)reg = LOAD.D(addr:address)
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emit "lfsd %out, %addr"
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cost 4;
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out:(int)ushort0 = LOADH.I(addr:address)
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emit "lhz %out, %addr"
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cost 4;
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out:(int)ubyte0 = LOADB.I(addr:address)
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emit "lbz %out, %addr"
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cost 4;
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/* ubyte intrinsics */
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out:(int)ubyteX = in:(int)ubyte0
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with %out == %in
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emit "! ubyte0 -> ubyteX"
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cost 1;
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out:(int)ubyte0 = in:(int)ubyteX
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emit "andi %out, %in, 0xff ! ubyteX -> ubyte0"
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cost 4;
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out:(int)reg = in:(int)ubyte0
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with %out == %in
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emit "! ubyte0 -> reg"
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cost 4;
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out:(int)ubyteX = in:(int)reg
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with %out == %in
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emit "! reg -> ubyteX"
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cost 1;
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/* ushort intrinsics */
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out:(int)ushortX = in:(int)ushort0
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with %out == %in
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emit "! ushort0 -> ushortX"
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cost 1;
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out:(int)ushort0 = in:(int)ushortX
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emit "andi %out, %in, 0xff ! ushortX -> ushort0"
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cost 4;
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out:(int)reg = in:(int)ushort0
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with %out == %in
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emit "! ushort0 -> reg"
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cost 4;
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out:(int)ushortX = in:(int)reg
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with %out == %in
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emit "! reg -> ushortX"
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cost 1;
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/* Extensions and conversions */
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out:(int)reg = EXTENDB.I(in:(int)reg)
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emit "extsb %out, %in"
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cost 4;
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out:(int)reg = EXTENDH.I(in:(int)reg)
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emit "extsh %out, %in"
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cost 4;
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out:(int)reg = FROMSI.I(in:(int)reg)
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with %out == %in
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emit "! FROMSI.I(int) -> int"
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cost 1;
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out:(int)reg = FROMUI.I(in:(int)reg)
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with %out == %in
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emit "! FROMUI.I(int) -> int"
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cost 1;
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out:(long)reg = FROMSI.L(in:(int)reg)
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emit "mr %out.0, %in"
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emit "srawi %out.1, %out.0, 31"
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cost 8;
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out:(int)reg = FROMD.I(in:(double)reg)
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with corrupted(volatile)
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emit "bl .fromd2i"
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cost 4;
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#if 0
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/* byte conversions */
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out:(int)ubyte0 = CIU14(in:(int)ubyte0)
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with %out == %in
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emit "! CIU14(ubyte0) -> ubyte0"
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cost 1;
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out:(int)ubyte0 = CIU41(in:(int)ubyte0)
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with %out == %in
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emit "! CIU41(ubyte0) -> ubyte0"
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cost 1;
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out:(int)ubyteX = CIU41(in:(int)ubyteX)
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with %out == %in
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emit "! CIU41(ubyteX) -> ubyteX"
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cost 1;
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out:(int)reg = CII14(in:(int)ubyteX)
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emit "extsb %out, %in ! CII14(ubyteX) -> reg"
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cost 4;
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/* short conversions */
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out:(int)ushort0 = CIU24(in:(int)ushort0)
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with %out == %in
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emit "! CIU24(ushort0) -> ushort0"
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cost 1;
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out:(int)ushort0 = CIU42(in:(int)ushort0)
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with %out == %in
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emit "! CIU42(ushort0) -> ushort0"
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cost 1;
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out:(int)ushortX = CIU42(in:(int)ushortX)
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with %out == %in
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emit "! CIU42(ushortX) -> ushortX"
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cost 1;
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out:(int)reg = CII24(in:(int)ushort0)
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with %out == %in
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emit "! CII24(ushort0) -> reg"
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cost 4;
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out:(int)reg = CII24(in:(int)ushortX)
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emit "extsh %out, %in"
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cost 4;
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#endif
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/* Locals */
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out:(int)reg = in:LOCAL.I
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emit "addi %out, fp, $in"
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cost 4;
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address = in:LOCAL.I
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emit "$in(fp)";
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/* Memory addressing modes */
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address = ADD.I(addr:(int)reg, offset:CONST.I)
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when signed_constant(%offset, 16)
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emit "$offset(%addr)";
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address = addr:(int)reg
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emit "0(%addr)";
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/* Branches */
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JUMP(addr:BLOCK.I)
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emit "b $addr"
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cost 4;
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CJUMPEQ(value:(cr)cr, PAIR(true:BLOCK.I, false:BLOCK.I))
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emit "bc 12, 2, $true" /* IFTRUE EQ */
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emit "b $false"
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cost 8;
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CJUMPLE(value:(cr)cr, PAIR(true:BLOCK.I, false:BLOCK.I))
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emit "bc 4, 1, $true" /* IFFALSE GT */
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emit "b $false"
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cost 8;
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CJUMPLT(value:(cr)cr, PAIR(true:BLOCK.I, false:BLOCK.I))
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emit "bc 12, 0, $true" /* IFTRUE LT */
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emit "b $false"
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cost 8;
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CALL(dest:LABEL.I)
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with corrupted(volatile)
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emit "bl $dest"
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cost 4;
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out:(ret)reg = CALL.I(dest:LABEL.I)
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with corrupted(volatile)
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emit "bl $dest"
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cost 4;
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out:(pret)reg = CALL.L(dest:LABEL.I)
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with corrupted(volatile)
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emit "bl $dest"
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cost 4;
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CALL(dest:(int)reg)
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with corrupted(volatile)
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emit "mtspr ctr, %dest"
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emit "bcctrl 20, 0, 0"
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cost 8;
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out:(ret)reg = CALL.I(dest:(int)reg)
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with corrupted(volatile)
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emit "mtspr ctr, %dest"
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emit "bcctrl 20, 0, 0"
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cost 8;
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out:(pret)reg = CALL.L(dest:(int)reg)
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with corrupted(volatile)
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emit "mtspr ctr, %dest"
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emit "bcctrl 20, 0, 0"
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cost 8;
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JUMP(dest:LABEL.I)
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emit "b $dest"
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cost 4;
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/* Comparisons */
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cr:(cr)cr = COMPARESI.I(left:(int)reg, right:(int)reg)
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emit "cmp %cr, 0, %left, %right"
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cost 4;
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cr:(cr)cr = COMPARESI.I(left:(int)reg, right:CONST.I)
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when signed_constant(%right, 16)
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emit "cmpi %cr, 0, %left, $right"
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cost 4;
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cr:(cr)cr = COMPAREUI.I(left:(int)reg, right:(int)reg)
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emit "cmpl %cr, 0, %left, %right"
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cost 4;
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cr:(cr)cr = COMPAREUI.I(left:(int)reg, right:CONST.I)
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when signed_constant(%right, 16)
|
|
emit "cmpli %cr, 0, %left, $right"
|
|
cost 4;
|
|
|
|
out:(cr)cr = COMPARESI.I(in:(cr)cr, result:CONST.I)
|
|
when specific_constant(%result, 0)
|
|
with %out == %in
|
|
emit "! COMPARESI.I(cr, 0)"
|
|
cost 4;
|
|
|
|
|
|
|
|
/* Booleans */
|
|
|
|
out:(int)reg = IFEQ.I(in:(cr)cr)
|
|
emit "mfcr %out" /* get cr0 */
|
|
emit "rlwinm %out, %out, [32-2], 2, 31" /* extract just EQ */
|
|
cost 8;
|
|
|
|
out:(int)reg = IFEQ.I(in:(int)reg)
|
|
emit "cntlzw %out, %in" /* returns 0..32 */
|
|
emit "rlwinm %out, %out, [32-5], 5, 31" /* if 32, return 1, otherwise 0 */
|
|
cost 8;
|
|
|
|
|
|
|
|
/* Conversions */
|
|
|
|
#if 0
|
|
out:(int)reg = CIU44(in:(int)reg)
|
|
with %out == %in
|
|
emit "! ciu44"
|
|
cost 4;
|
|
|
|
out:(int)reg = CUI44(in:(int)reg)
|
|
with %out == %in
|
|
emit "! cui44"
|
|
cost 4;
|
|
#endif
|
|
|
|
/* ALU operations */
|
|
|
|
#define ALUR(name, instr) \
|
|
out:(int)reg = name(left:(int)reg, right:(int)reg) \
|
|
emit instr " %out, %left, %right" \
|
|
cost 4; \
|
|
|
|
#define ALUC(name, instr) \
|
|
out:(int)reg = name(left:(int)reg, right:CONST.I) \
|
|
when signed_constant(%right, 16) \
|
|
emit instr " %out, %left, $right" \
|
|
cost 4; \
|
|
|
|
#define ALUC_reversed(name, instr) \
|
|
out:(int)reg = name(left:CONST.I, right:(int)reg) \
|
|
when signed_constant(%left, 16) \
|
|
emit instr " %out, %right, $left" \
|
|
cost 4; \
|
|
|
|
#define ALUCC(name, instr) \
|
|
ALUC(name, instr) \
|
|
ALUC_reversed(name, instr)
|
|
|
|
ALUR(ADD.I, "add")
|
|
ALUCC(ADD.I, "addi")
|
|
|
|
out:(int)reg = SUB.I(left:(int)reg, right:(int)reg)
|
|
emit "subf %out, %left, %right"
|
|
cost 4;
|
|
|
|
out:(int)reg = SUB.I(left:(int)reg, right:CONST.I)
|
|
emit "addi %out, %left, -[$right]"
|
|
cost 4;
|
|
|
|
out:(int)reg = MOD.I(left:(int)reg, right:(int)reg)
|
|
emit "divw %out, %left, %right"
|
|
emit "mullw %out, %out, %right"
|
|
emit "subf %out, %out, %left"
|
|
cost 12;
|
|
|
|
out:(int)reg = MODU.I(left:(int)reg, right:(int)reg)
|
|
emit "divwu %out, %left, %right"
|
|
emit "mullw %out, %out, %right"
|
|
emit "subf %out, %out, %left"
|
|
cost 12;
|
|
|
|
ALUR(MUL.I, "mullw")
|
|
ALUCC(MUL.I, "mulli")
|
|
|
|
ALUR(DIV.I, "divw")
|
|
ALUR(DIVU.I, "divwu")
|
|
|
|
ALUR(ASL.I, "slw")
|
|
|
|
ALUR(LSL.I, "slw")
|
|
|
|
out:(int)reg = NEG.I(left:(int)reg)
|
|
emit "neg %out, %left"
|
|
cost 4;
|
|
|
|
out:(int)reg = NOT.I(left:(int)reg)
|
|
emit "cntlzw %out, %left"
|
|
emit "rlwinm %out, %out, 32-5, 5, 31"
|
|
cost 8;
|
|
|
|
ALUR(AND.I, "and")
|
|
ALUCC(AND.I, "andi.")
|
|
|
|
ALUR(OR.I, "or")
|
|
ALUCC(OR.I, "ori")
|
|
|
|
ALUR(EOR.I, "xor")
|
|
ALUCC(EOR.I, "xori")
|
|
|
|
out:(int)reg = value:LABEL.I
|
|
emit "la %out, $value"
|
|
cost 4;
|
|
|
|
out:(int)reg = value:BLOCK.I
|
|
emit "la %out, $value"
|
|
cost 4;
|
|
|
|
out:(int)reg = value:CONST.I
|
|
emit "li %out, $value"
|
|
cost 8;
|
|
|
|
|
|
/* FPU operations */
|
|
|
|
#define FPU4R(name, instr) \
|
|
out:(float)reg = name(left:(float)reg, right:(float)reg) \
|
|
emit instr " %out, %left, %right" \
|
|
cost 4; \
|
|
|
|
#define FPU8R(name, instr) \
|
|
out:(double)reg = name(left:(double)reg, right:(double)reg) \
|
|
emit instr " %out, %left, %right" \
|
|
cost 4; \
|
|
|
|
out:(float)reg = LOAD.F(addr:address)
|
|
emit "lfs %out, %addr"
|
|
cost 4;
|
|
|
|
out:(double)reg = LOAD.D(addr:address)
|
|
emit "lfd %out, %addr"
|
|
cost 4;
|
|
|
|
out:(float)reg = value:CONST.F
|
|
emit "lfs %out, address-containing-$value"
|
|
cost 8;
|
|
|
|
FPU4R(ADDF.F, "fadds")
|
|
FPU8R(ADDF.D, "fadd")
|
|
|
|
FPU4R(SUBF.F, "fsubs")
|
|
FPU8R(SUBF.D, "fsub")
|
|
|
|
FPU4R(MULF.F, "fmuls")
|
|
FPU8R(MULF.D, "fmul")
|
|
|
|
FPU4R(DIVF.F, "fdivs")
|
|
FPU8R(DIVF.D, "fdiv")
|
|
|
|
out:(float)reg = NEGF.F(left:(float)reg)
|
|
emit "fneg %out, %left"
|
|
cost 4;
|
|
|
|
out:(double)reg = NEGF.D(left:(double)reg)
|
|
emit "fneg %out, %left"
|
|
cost 4;
|
|
|
|
cr:(cr)cr = COMPAREF.I(left:(float)reg, right:(float)reg)
|
|
emit "fcmpu %cr, %left, %right"
|
|
cost 4;
|
|
|
|
cr:(cr)cr = COMPARED.I(left:(double)reg, right:(double)reg)
|
|
emit "fcmpu %cr, %left, %right"
|
|
cost 4;
|
|
|
|
#if 0
|
|
out:(ret)reg = CFI44(val:(fret)reg)
|
|
with corrupted(volatile)
|
|
emit "bl .cfi44"
|
|
cost 4;
|
|
|
|
out:(fret)reg = CIF44(val:(ret)reg)
|
|
with corrupted(volatile)
|
|
emit "bl .cif44"
|
|
cost 4;
|
|
|
|
out:(ret)reg = CFI84(val:(dret)reg)
|
|
with corrupted(volatile)
|
|
emit "bl .cfi84"
|
|
cost 4;
|
|
|
|
out:(dret)reg = CIF48(val:(ret)reg)
|
|
with corrupted(volatile)
|
|
emit "bl .cif48"
|
|
cost 4;
|
|
|
|
out:(float)reg = CFF84(val:(double)reg)
|
|
emit "frsp %out, %val"
|
|
cost 4;
|
|
|
|
out:(double)reg = CFF48(val:(float)reg)
|
|
emit "fmr %out, %val"
|
|
cost 1;
|
|
#endif
|
|
|
|
/* vim: set sw=4 ts=4 expandtab : */
|
|
|