146 lines
4 KiB
C
146 lines
4 KiB
C
/*
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* (c) copyright 1987 by the Vrije Universiteit, Amsterdam, The Netherlands.
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* See the copyright notice in the ACK home directory, in the file "Copyright".
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*/
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#define RCSID1 "$Id$"
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/*
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* NS 16032 C declarations
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*/
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#define low4(val) ((int)(val&0xF))
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/* signed value fits in ? bits */
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#define fit32(val) ( (val)>= -2147483647L-1 && (val)<=2147483647L )
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#define fit16(val) ( (val)>= -32767-1 && (val)<=32767 )
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#define fit8(val) ( (val)>= -128 && (val)<=127 )
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#define fit4(val) ( (val)>= -8 && (val)<=7 )
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/* Fits in byte, word displacement */
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#define fitd_b(val) ( (val)>= -64 && (val)<=63 )
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#define fitd_w(val) ( (val)>= -8192 && (val)<=8191 )
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/* Assemble and disassemble operator id's */
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/* the i_value's in the instruction keyword table
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contain five bit fields:
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0-3 Opcode used in format indicated by the i_type field
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4-7 Condition Code field. B_?? Also used for reg in FFS type.
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8-11 The type of the first addressing mode gen1
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12-15 The type of the second addressing mode gen2
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The integer type T_????
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The custom Slave type S_????
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The Floating point type F_????
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*/
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#define MK_op(op) (op)
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#define MK_cc(cc) ( (cc)<<4 )
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#define MK_g1(g1) ( (g1)<<8 )
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#define MK_g2(g2) ( (g2)<<12 )
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#define mk_op(o) (MK_op(o)|MK_g1(X_ILLGL)|MK_g2(X_ILLGL))
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#define mk_op1(o,g1) (MK_op(o)|MK_g1(g1)|MK_g2(X_ILLGL))
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#define mk_op2(o,g1,g2) (MK_op(o)|MK_g1(g1)|MK_g2(g2))
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#define mk_c(c) MK_cc(c)
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#define mk_op1c(o,g1,c) (MK_op(o)|MK_g1(g1)|MK_g2(X_ILLGL)|MK_cc(c))
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#define mk_op2c(o,g1,g2,c) (MK_op(o)|MK_g1(g1)|MK_g2(g2)|MK_cc(c))
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#define id_op(id) ((id) &0xF)
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#define id_cc(id) (((id)>>4) &0xF)
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#define id_g1(id) (((id)>>8) &3)
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#define id_g2(id) (((id)>>12)&3)
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#define id_t1(id) (((id)>>10)&3)
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#define id_t2(id) (((id)>>14)&3)
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/* Type definitions */
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#define T_INT 0
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#define T_FL 1
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#define T_SLAVE 2
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#define T_ILLGL 3
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#define I_BYTE (T_INT<<2) | 0
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#define I_WORD (T_INT<<2) | 1
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#define I_DOUBLE (T_INT<<2) | 3
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#define F_FLOAT (T_FL<<2) | 1
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#define F_LONG (T_FL<<2) | 0
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#define S_DOUBLE (T_SLAVE<<2) | 1
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#define S_QUAD (T_SLAVE<<2) | 0
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#define X_ILLGL (T_ILLGL<<2) | 2
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#define B_EQ 0x0
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#define B_NE 0x1
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#define B_CS 0x2
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#define B_CC 0x3
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#define B_HI 0x4
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#define B_LS 0x5
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#define B_GT 0x6
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#define B_LE 0x7
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#define B_FS 0x8
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#define B_FC 0x9
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#define B_LO 0xA
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#define B_HS 0xB
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#define B_LT 0xC
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#define B_GE 0xD
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#define B_TRUE 0xE
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#define B_FALSE 0xF
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/* String option bits */
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#define SO_UNTIL 0xC
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#define SO_WHILE 0x4
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#define SO_BACKW 0x2
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#define SO_TRANS 0x1
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/* output definitions */
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#define form0(id) emit1(0xA + (id_cc(id)<<4) )
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#define form1(id) emit1(0x2 + (id_op(id)<<4) )
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#define form6(id) emit1(0x4E) ; form4(id)
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#define form7(id) emit1(0xCE) ; form4(id)
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/* Structure contains information for generation of an addressing mode */
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/* The size of immediates is not stored in here and must be fetched from
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a id-field
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*/
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extern struct {
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int m_mode; /* The main mode bits */
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int m_index ; /* m_mode= index mode, m_index has index byte */
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int m_ndisp ; /* The number of displacements */
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expr_t m_expr1 ; /* The first expression */
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#ifdef RELOCATION
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int m_rel1, m_rel2; /* relocation */
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#endif
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expr_t m_expr2 ; /* The second expression */
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} mode1, mode2, *mode_ptr ;
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#define not_imm(mode_ptr) if ( (mode_ptr)->m_mode==0x14 ) ill_imm() ;
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/* NS Specific routines */
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void clrmode(void);
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int ind_mode(int type);
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void badsyntax(void);
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void ill_imm(void);
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void form2(int id, int sval);
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void form3(int id);
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void form4(int id);
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void form5(int id, int sval);
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void form7x(int id,int i_type);
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void form8(int id,int reg);
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void form9(int id,int i_type,int f_type);
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void form11(int id);
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void form14(int id,int reg);
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void frm15_0(int id,int reg);
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void frm15_1(int id,int i_type,int s_type);
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void frm15_5(int id);
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void gen1(int id);
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void gengen(int id);
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void disp(register expr_t *expr, int relpc);
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void putdisp(valu_t val,int size);
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void dot_adjust(register expr_t *expr);
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int testsize(int type,int val);
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void imm(int i_type,register expr_t *expr);
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int reg_list(int list,int reverse);
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int cpu_opt(int indic);
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int string_opt(int indic);
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