b1badf1851
Add more page numbers from PowerPC version 2.01. Remove "xnop" not in 2.01, add "mtcr" from 2.01. Add "lwarx" and the other instructions from Book II. I did not try all the newly added instructions, but these seem to work: dcbt, dcbtst, icibi, isync, lwarx, stwcx., mftb, mftbu In man/powerpc_as.6 (not installed), add a summary of the registers and addressing modes (like in i386_as.6), describe short forms, update description of hi16/ha16, add CAVEATS about instructions that some processors can't run.
137 lines
4.9 KiB
Groff
137 lines
4.9 KiB
Groff
.TH POWERPC_AS 1 2018-03-07
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.ad
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.SH NAME
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powerpc_as \- assembler for PowerPC
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.SH SYNOPSIS
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as [options] argument ...
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.SH DESCRIPTION
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This assembler is made with the general framework
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described in \fIuni_ass\fP(6).
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.PP
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It can assemble the instructions from Book I and Book II of PowerPC
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version 2.01.
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This includes the branch, integer, and floating point instructions
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from Book I; and the cache, synchronization, and time base
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instructions from Book II.
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.PP
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There is no support for other instructions, such as supervisor-mode
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instructions or vector instructions.
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There is some support for 64-bit integer instructions, but the
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assembler only has 32-bit symbols.
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.SH SYNTAX
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.SS general purpose registers
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There are 32 GPRs from \fBr0\fP to \fBr31\fP.
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In this assembler, \fBsp\fP is an alias for \fBr1\fP, and \fBfp\fP is
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an alias for \fBr2\fP, because \fIack\fP uses r1 as the stack pointer
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and r2 as the frame pointer.
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Other compilers don't use r2 as the frame pointer.
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.PP
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GPR syntax requires a register name, not a number.
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For example, \(oqaddi\ r5,\ r4,\ 1\(cq works, but
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\(oqaddi\ 5,\ 4,\ 1\(cq is a syntax error.
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.PP
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Certain instructions ignore the contents of \fBr0\fP and use zero.
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This happens when using r0 as the second operand of \fIaddi\fP or
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\fIaddis\fP, or when addressing \(oqexpr(r0)\(cq or
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\(oqr0,\ gpr\(cq.
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The syntax is still the name r0, not the number 0.
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.SS floating point registers
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There are 32 FPRs from \fBf0\fP to \fBf31\fP.
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Each FPR has 64 bits and can hold a single-precision or
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double-precision number.
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FPR syntax requires a register name, not a number.
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.SS special purpose registers
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The three named SPRs are \fBctr\fP (count register), \fBlr\fP (link
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register), and \fBxer\fP (exception register).
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\(oqmfspr\(cq and \(oqmtspr\(cq allow these names or a number.
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.SS condition register
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There is a 32-bit condition register, where bit 0 is most significant,
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and bit 31 is least significant.
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This gets split into 8 registers of 4 bits each, from \fBcr0\fP (with
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bits 0 to 3) to \fBcr7\fP (with bits 28 to 31).
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Some instructions use the names cr0 to cr7, others use a bit numbered
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0 to 31, and others use all 32 bits.
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.SS addressing modes
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\(oqexpr(gpr)\(cq addresses \fIexpr\fP + the contents of \fIgpr\fP,
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except that \(oqexpr(r0)\(cq addresses \fIexpr\fP\ +\ 0.
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A few instructions, like \(oqstwu\(cq, also update \fIgpr\fP by
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setting it to the address.
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.PP
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\(oqgprA,\ gprB\(cq in certain instructions addresses the contents of
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\fIgprA\fP + the contents of \fIgprB\fP, except that \(oqr0,\ gprB\(cq
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addresses 0\ +\ the contents of \fIgprB\fP.
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.SS 16-bit operands
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Some instructions have a 16-bit operand.
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This can be a bare \fIexpr\fP (which must fit signed or unsigned
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16 bits), or it can be one of these special functions:
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.IP "hi16[expr], ha16[expr]"
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Returns the high half of the 32-bit value of the expression.
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If the low half is negative (from 0x8000 to 0xffff),
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then \fBha16[]\fP adjusts the high half by adding 1.
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Use \fBhi16[]\fP if the instruction with \fBlo16[]\fP is going to
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interpret its operand as an unsigned value, or \fBha16[]\fP if it will
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interpret it as signed.
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.IP
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If \fIexpr\fP is not absolute, then the assembler must generate a
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fixup for the linker.
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The fixup only works if the instruction is
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\(oqaddis gpr, r0, hx16[expr]\(cq or \(oqlis gpr, hx16[expr]\(cq.
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.IP lo16[expr]
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Returns the low half of the 32-bit value of the expression.
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.SS short forms
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Some instructions have short forms using extended mnemonics (or
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simplified mnemonics) like \fIli\fP, \fIsrwi\fP, and many others.
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.IP "li r6, 789"
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is short for: addi r6, r0, 789
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.IP "srwi r3, r4, 2"
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is short for: rlwinm r3, r4, 30, 2, 31
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.PP
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This assembler doesn't support extended mnemonics with branch
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prediction, such as \fIblt+\fP or \fIbne-\fP.
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It always parses \(oq+\(cq and \(oq-\(cq as operators,
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never as part of a mnemonic.
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.SH EXAMPLES
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There are two ways to load r3 with _symbol\ =\ 0x1234abcd.
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One way is
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.PP
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.nf
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lis r3, hi16[_symbol]
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ori r3, r3, lo16[_symbol] ! r3 = 0x12340000 | 0x0000abcd
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.fi
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.PP
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The other way is
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.PP
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.nf
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lis r3, ha16[_symbol]
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addi r3, r3, lo16[_symbol] ! r3 = 0x12350000 + 0xffffabcd
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.fi
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.PP
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The next code adds 1 to a global variable.
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.PP
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.nf
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lis r3, ha16[_var]
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lwz r4, lo16[_var](r3)
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addi r4, r4, 1
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stw r4, lo16[_var](r3)
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.fi
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.SH "SEE ALSO"
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uni_ass(6),
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ack(1)
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.PP
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Freescale Semiconductor, \fIProgramming Environments Manual for 32-Bit
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Implementations of the PowerPC Architecture\fP, Rev. 3, September 2005.
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.PP
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IBM, \fIPowerPC User Instruction Set Architecture, Book I\fP, Version
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2.01, September 2003.
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.PP
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IBM, \fIPowerPC Virtual Environment Architecture, Book II\fP, Version
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2.01, December 2003.
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.SH CAVEATS
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Beware that not every processor can run every instruction.
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The 32-bit processors can't run 64-bit instructions like \fIlwa\fP,
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\fIstd\fP, and \fIfctid\fP.
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The PowerPC 601 can't run \fIstfiwx\fP, nor \fIfres\fP, \fIfrsqrte\fP,
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\fIfsel\fP.
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Many models, like the PowerPC G4, can't run \fIfsqrt\fP nor
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\fIfsqrts\fP.
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