b8c921ca70
PowerPC has a few hundred special-purpose registers. The assembler had only accepted the names "xer", "lr", "ctr". Most programs use only those three SPRs. If I add more names, they would almost never get used, and they might conflict with labels. I want to use "mfspr r3, 0x3f0" and "mtspr 0x3f0, r3" in plat/qemu/boot.s to access register hid0 from supervisor mode.
250 lines
8.2 KiB
C
250 lines
8.2 KiB
C
/*
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* $Source$
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* $State$
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*/
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operation
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: OP_BF_BFA CR ',' CR { emit4($1 | ($2<<23) | ($4<<18)); }
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| OP_BF_FRA_FRB CR ',' FPR ',' FPR { emit4($1 | ($2<<23) | ($4<<16) | ($6<<11)); }
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| OP_BF_L_RA_RB CR ',' u1 ',' GPR ',' GPR { emit4($1 | ($2<<23) | ($4<<21) | ($6<<16) | ($8<<11)); }
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| OP_BF_L_RA_SI CR ',' u1 ',' GPR ',' e16 { emit4($1 | ($2<<23) | ($4<<21) | ($6<<16) | $8); }
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| OP_BF_L_RA_UI CR ',' u1 ',' GPR ',' e16 { emit4($1 | ($2<<23) | ($4<<21) | ($6<<16) | $8); }
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| OP_BF_U_C c CR ',' u4 { emit4($1 | $2 | ($3<<23) | ($5<<12)); }
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| OP_BO_BI_BDA u5 ',' u5 ',' bda { emit4($1 | ($2<<21) | ($4<<16) | $6); }
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| OP_BO_BI_BDL u5 ',' u5 ',' bdl { emit4($1 | ($2<<21) | ($4<<16) | $6); }
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| OP_BO_BI_BH u5 ',' u5 ',' u2 { emit4($1 | ($2<<21) | ($4<<16) | ($6<<11)); }
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| OP_BT_BA_BB u5 ',' u5 ',' u5 { emit4($1 | ($2<<21) | ($4<<16) | ($6<<11)); }
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| OP_BT_C c u5 { emit4($1 | $2 | ($3<<21)); }
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| OP_FLM_FRB_C c u8 ',' FPR { emit4($1 | $2 | ($3<<17) | ($5<<11)); }
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| OP_FRS_RA_D FPR ',' e16 '(' GPR ')' { emit4($1 | ($2<<21) | ($6<<16) | $4); }
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| OP_FRS_RA_RB FPR ',' GPR ',' GPR { emit4($1 | ($2<<21) | ($4<<16) | ($6<<11)); }
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| OP_FRT_FRA_FRB_C c FPR ',' FPR ',' FPR { emit4($1 | $2 | ($3<<21) | ($5<<16) | ($7<<11)); }
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| OP_FRT_FRA_FRC_FRB_C c FPR ',' FPR ',' FPR ',' FPR { emit4($1 | $2 | ($3<<21) | ($5<<16) | ($9<<11) | ($7<<6)); }
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| OP_FRT_FRA_FRC_C c FPR ',' FPR ',' FPR { emit4($1 | $2 | ($3<<21) | ($5<<16) | ($7<<6)); }
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| OP_FRT_FRB_C c FPR ',' FPR { emit4($1 | $2 | ($3<<21) | ($5<<11)); }
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| OP_FRT_RA_D FPR ',' e16 '(' GPR ')' { emit4($1 | ($2<<21) | ($6<<16) | $4); }
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| OP_FRT_RA_RB FPR ',' GPR ',' GPR { emit4($1 | ($2<<21) | ($4<<16) | ($6<<11)); }
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| OP_FRT_C c FPR { emit4($1 | $2 | ($3<<21)); }
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| OP_RT GPR { emit4($1 | ($2<<21)); }
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| OP_RT_RA_C c GPR ',' GPR { emit4($1 | $2 | ($3<<21) | ($5<<16)); }
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| OP_RT_RA_D GPR ',' e16 '(' GPR ')' { emit4($1 | ($2<<21) | ($6<<16) | $4); }
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| OP_RT_RA_DS GPR ',' ds '(' GPR ')' { emit4($1 | ($2<<21) | ($6<<16) | $4); }
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| OP_RT_RA_NB GPR ',' GPR ',' nb { emit4($1 | ($2<<21) | ($4<<16) | ($6<<11)); }
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| OP_RT_RA_RB GPR ',' GPR ',' GPR { emit4($1 | ($2<<21) | ($4<<16) | ($6<<11)); }
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| OP_RT_RA_RB_C c GPR ',' GPR ',' GPR { emit4($1 | $2 | ($3<<21) | ($5<<16) | ($7<<11)); }
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| OP_RT_RA_SI GPR ',' GPR ',' e16 { emit4($1 | ($2<<21) | ($4<<16) | $6); }
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| OP_RT_RA_SI_addic c GPR ',' GPR ',' e16 { emit4($1 | ($2<<26) | ($3<<21) | ($5<<16) | $7); }
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| OP_RT_SPR GPR ',' spr_num { emit4($1 | ($2<<21) | ($4<<11)); }
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| OP_RS_FXM u7 ',' GPR { emit4($1 | ($4<<21) | ($2<<12)); }
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| OP_RS_RA_C c GPR ',' GPR { emit4($1 | $2 | ($5<<21) | ($3<<16)); }
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| OP_RS_RA_D GPR ',' e16 '(' GPR ')' { emit4($1 | ($2<<21) | ($6<<16) | $4); }
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| OP_RS_RA_DS GPR ',' ds '(' GPR ')' { emit4($1 | ($2<<21) | ($6<<16) | $4); }
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| OP_RS_RA_NB GPR ',' GPR ',' nb { emit4($1 | ($2<<21) | ($4<<16) | ($6<<11)); }
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| OP_RS_RA_UI GPR ',' GPR ',' e16 { emit4($1 | ($4<<21) | ($2<<16) | $6); }
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| OP_RS_RA_UI_CC C GPR ',' GPR ',' e16 { emit4($1 | ($5<<21) | ($3<<16) | $7); }
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| OP_RS_RA_RB GPR ',' GPR ',' GPR { emit4($1 | ($2<<21) | ($4<<16) | ($6<<11)); }
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| OP_RS_RA_RB_C c GPR ',' GPR ',' GPR { emit4($1 | $2 | ($5<<21) | ($3<<16) | ($7<<11)); }
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| OP_RS_RA_RA_C c GPR ',' GPR { emit4($1 | $2 | ($5<<21) | ($3<<16) | ($5<<11)); }
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| OP_RS_RA_RB_MB5_ME5_C c GPR ',' GPR ',' GPR ',' u5 ',' u5 { emit4($1 | $2 | ($5<<21) | ($3<<16) | ($7<<11) | ($9<<6) | ($11<<1)); }
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| OP_RS_RA_RB_MB6_C c GPR ',' GPR ',' GPR ',' u6 { emit4($1 | $2 | ($5<<21) | ($3<<16) | ($7<<11) | (($9&0x1F)<<6) | (($9&0x20)>>0)); }
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| OP_RS_RA_RB_ME6_C c GPR ',' GPR ',' GPR ',' u6 { emit4($1 | $2 | ($5<<21) | ($3<<16) | ($7<<11) | (($9&0x1F)<<6) | (($9&0x20)>>0)); }
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| OP_RS_RA_SH_MB5_ME5_C c GPR ',' GPR ',' u5 ',' u5 ',' u5 { emit4($1 | $2 | ($5<<21) | ($3<<16) | ($7<<11) | ($9<<6) | ($11<<1)); }
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| OP_RS_RA_SH_MB6_SH_C c GPR ',' GPR ',' u6 ',' u6 { emit4($1 | $2 | ($5<<21) | ($3<<16) | (($7&0x1F)<<11) | ($9<<6) | (($7&0x20)>>4)); }
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| OP_RS_RA_SH_ME6_SH_C c GPR ',' GPR ',' u6 ',' u6 { emit4($1 | $2 | ($5<<21) | ($3<<16) | (($7&0x1F)<<11) | ($9<<6) | (($7&0x20)>>4)); }
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| OP_RS_RA_SH5_C c GPR ',' GPR ',' u5 { emit4($1 | $2 | ($5<<21) | ($3<<16) | ($7<<11)); }
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| OP_RS_RA_SH6_C c GPR ',' GPR ',' u6 { emit4($1 | $2 | ($5<<21) | ($3<<16) | (($7&0x1F)<<11) | (($7&0x20)>>4)); }
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| OP_RS_SPR spr_num ',' GPR { emit4($1 | ($4<<21) | ($2<<11)); }
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| OP_TO_RA_RB u5 ',' GPR ',' GPR { emit4($1 | ($2<<21) | ($4<<16) | ($6<<11)); }
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| OP_TO_RA_SI u5 ',' GPR ',' e16 { emit4($1 | ($2<<21) | ($4<<16) | $6); }
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| OP_LEV u7 { emit4($1 | ($2<<5)); }
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| OP_LIA lia { emit4($1 | $2); }
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| OP_LIL lil { emit4($1 | $2); }
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| OP_LI32 li32 /* emitted in subrule */
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;
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c
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: /* nothing */ { $$ = 0; }
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| C { $$ = 1; }
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;
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e16
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: absexp
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{
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/* Allow signed or unsigned 16-bit values. */
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if (($1 < -0x8000) || ($1 > 0xffff))
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serror("16-bit value out of range");
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$$ = (uint16_t) $1;
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}
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;
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u8
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: absexp
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{
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if (($1 < 0) || ($1 > 0xFF))
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serror("8-bit unsigned value out of range");
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$$ = $1;
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}
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;
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u7
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: absexp
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{
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if (($1 < 0) || ($1 > 0x7F))
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serror("7-bit unsigned value out of range");
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$$ = $1;
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}
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;
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u6
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: absexp
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{
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if (($1 < 0) || ($1 > 0x3F))
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serror("6-bit unsigned value out of range");
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$$ = $1;
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}
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;
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u5
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: absexp
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{
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if (($1 < 0) || ($1 > 0x1F))
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serror("5-bit unsigned value out of range");
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$$ = $1;
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}
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;
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u4
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: absexp
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{
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if (($1 < 0) || ($1 > 0xF))
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serror("4-bit unsigned value out of range");
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$$ = $1;
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}
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;
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u1
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: absexp
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{
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if (($1 < 0) || ($1 > 1))
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serror("1-bit unsigned value out of range");
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$$ = $1;
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}
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;
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u2
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: absexp
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{
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if (($1 < 0) || ($1 > 0x3))
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serror("2-bit unsigned value out of range");
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$$ = $1;
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}
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;
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ds
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: e16
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{
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if ($1 & 3)
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serror("value must be 4-aligned");
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$$ = $1;
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}
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;
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nb
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: absexp
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{
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if (($1 < 1) || ($1 > 32))
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serror("register count must be in the range 1..32");
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if ($1 == 32)
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$$ = 0;
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else
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$$ = $1;
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}
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;
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bdl
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: expr
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{
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int dist = $1.val - DOTVAL;
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fit(fitx(dist, 25));
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if (dist & 0x3)
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serror("jump targets must be 4-aligned");
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DOTVAL += 2;
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newrelo($1.typ, RELO2 | RELPC | FIXUPFLAGS);
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DOTVAL -= 2;
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$$ = dist & 0xFFFD;
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}
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;
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bda
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: expr
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{
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int target = $1.val;
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fit(fitx(target, 16));
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if (target & 0x3)
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serror("jump targets must be 4-aligned");
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DOTVAL += 2;
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newrelo($1.typ, RELO2 | FIXUPFLAGS);
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DOTVAL -= 2;
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$$ = target & 0xFFFD;
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}
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;
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li32
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: GPR ',' expr
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{
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quad type = $3.typ & S_TYP;
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quad val = $3.val;
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if ((type == S_ABS) && (val <= 0xffff))
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emit4((14<<26) | ($1<<21) | (0<<16) | val); /* addi */
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else
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{
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newrelo($3.typ, RELOPPC | FIXUPFLAGS);
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emit4((15<<26) | ($1<<21) | (0<<16) | (val >> 16)); /* addis */
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emit4((24<<26) | ($1<<21) | ($1<<16) | (val & 0xffff)); /* ori */
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}
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}
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;
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lil
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: expr
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{
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int dist = $1.val - DOTVAL;
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fit(fitx(dist, 26));
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if (dist & 0x3)
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serror("jump targets must be 4-aligned");
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newrelo($1.typ, RELOPPC | RELPC | FIXUPFLAGS);
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$$ = dist & 0x03FFFFFD;
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}
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;
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lia
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: expr
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{
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int target = $1.val;
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fit(fitx(target, 26));
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if (target & 0x3)
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serror("jump targets must be 4-aligned");
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newrelo($1.typ, RELOPPC | FIXUPFLAGS);
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$$ = target & 0x03FFFFFD;
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}
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;
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spr_num
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: SPR { $$ = $1; }
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| absexp
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{
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if (($1 < 0) || ($1 > 0x3ff))
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serror("spr number out of range");
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/* mfspr, mtspr swap the low and high 5 bits */
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$$ = ($1 >> 5) | (($1 & 0x1f) << 5);
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}
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;
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