148 lines
4.2 KiB
Groff
148 lines
4.2 KiB
Groff
.TH NS_ASS VI
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.ad
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.SH NAME
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ns_as \- National Semiconductor 16032 assembler/linker
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.SH SYNOPSIS
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\&..../lib/ns/as [options] argument ...
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.SH DESCRIPTION
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The assembler for the National Semiconductor 16032 is based
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on the universal assembler \fIuni_ass\fP(VI).
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The mnemonics for the instructions are taken from the NS-16000
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Programmers Reference Manual.
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The syntax of the instruction operands is similar to the syntax used
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in that manual,
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although the meaning is sometimes quite different.
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The cross assembler issued by National Semiconductor
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associates a type (sb,..) with each symbol
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and automatically generates sb offset mode for symbols of type sb.
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This assembler does not record the types,
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each symbol simply produces an untyped value.
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.sp 1
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The possible operands are:
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.IP "general registers
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These are called r0, r1, r2, r3, r4, r5, r6 and r7.
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The symbol REG is used to indicate use of any of these 8 registers
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in other operands.
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.IP "floating point registers
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These are called f0, f1, f2, f3, f4, f5, f6 and f7.
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.IP "dedicated registers
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All types of dedicated registers can be used with the appropriate instructions.
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Examples: sb, fp, intbase, ptb1.
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.IP expr(REG)
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register relative
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.IP expr(fp)
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frame pointer relative
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.IP expr(sb)
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static base relative
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.IP expr(sp)
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stack pointer relative
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.IP expr(pc)
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program counter relative,
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the expression indicates a location in memory from which the current value
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of '.' is subtracted by the assembler.
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E.g. "movw label(pc),r0; label: .word ..." moves the contents of the word
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at \fIlabel\fP to r0.
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.IP expr(expr(fb))
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.IP expr(expr(sb))
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.IP expr(expr(sp))
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memory relative
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.IP @expr
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absolute
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.IP external(expr)+expr
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The external mode is provided, although this assembler
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does not build a module table.
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.IP tos
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top of stack.
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.PD 0
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.sp 1
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.PP
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Usage of the scaled index operands is allowed.
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.br
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The convention used to indicate offset length by appending :B, :W or :D
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to offsets is not implemented.
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The assembler tries to find out the minimal size needed for any constant
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in an operand of the instruction placed in the text segment.
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Offsets in instructions outside \fI.text\fP are always four bytes.
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.PP
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All special operands, e.g. register list, configuration list, have
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the same format as in the Programmers Reference Manual.
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.PP
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Whenever possible the assembler automatically uses the short(quick) opcodes for
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jsr(jsb), jump(br), add(addq), cmp(cmpq) and mov(movq).
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.SH BUGS
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The data types floating and packed-decimal are not supported.
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.br
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Initialization of floating-point numbers is not possible.
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.br
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The mnemonics of the slave processor instructions are poorly documented,
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the format of the NS-16032S-6 data sheet is used.
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.br
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The documentation gave contradictory information on the format
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of a few instructions.
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.IP -
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Three different schemes are presented for the encoding
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of the last operand of the block instructions.
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.IP -
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Two different values are specified for
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the encoding of the msr register in smr and lmr instructions.
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.IP -
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Two different possibilities are given for the encoding of
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the instructions movsu and movus.
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.SH EXAMPLE
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.nf
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.ta 12n 20n 28n 36n
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00000000 0E0B02 setcfg [ m ]
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label:
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00000003 EC3E lprb psr,r7
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00000005 2D37 sprw intbase,r6
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00000007 EA7C br label
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00000009 02803B bsr rout1
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0000000C 228044 cxp rout1
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0000000F 1204 ret 4
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00000011 4204 rett 4
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00000013 328044 rxp rout1
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00000016 1E0300 rdval r0
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00000019 163028 scsr r5
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0000001C 3F32 shid r6
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0000001E 7F0B bispsrd r1
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00000020 7C17 caseb r2
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00000022 7FA806 cxpd @6
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00000025 021F jsr @rout1
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00000027 BEB529 absf f5,f6
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0000002A EE0538 movusw r7,r0
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0000002D 3E40A101 movbl 1,f5
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00000031 CE440003 cmpmb r0,r1,4
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00000035 CE4F0800 extsd r1,r1,0,1
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00000039 62A0 save [ r5, r7 ]
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0000003B 1E0B00 lmr bpr0,r0
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0000003E 0E8C04 skpst w
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00000041 CC0042 acbb 1,r0,label
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00000044 B2 rout1: wait
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00000045 7F950C0B adjspd 11(12(sb))
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00000049 7CA50D adjspb 13
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0000004C 7DB50102 adjspw external(1)+2
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00000050 7FBD adjspd tos
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00000052 7CED860807 adjspb 7(8(fp))[r6:w]
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.fi
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.SH "SEE ALSO"
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uni_ass(VI)
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.br
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NS 16000 Programmers Reference Manual. Publ. no. 420306565-001PB
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.br
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NS16032S-6, NS16032S-4 High Performance Microprocessors, november 1982
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.br
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publ. no. 420306619-002A.
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.PD 0
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.SH AUTHOR
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Ed Keizer, Vrije Universiteit
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