145 lines
3.3 KiB
Groff
145 lines
3.3 KiB
Groff
.\" $Header$
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.TH I86_AS 1
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.ad
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.SH NAME
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i86_as \- assembler for Intel 8086
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.SH SYNOPSIS
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/usr/em/lib/i86_as [options] argument ...
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.SH DESCRIPTION
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This assembler is made with the general framework
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described in \fIuni_ass\fP(6).
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.SH SYNTAX
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.IP segments
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An address on the Intel 8086 consists of two pieces:
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a segment number and an offset. A memory address is computed as
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the segment number shifted left 4 bits + the offset.
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Assembly language addresses only give the offset, with the exception of
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the address of an inter-segment jump or call (see \fIaddressing modes\fP
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below).
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For each segment type (.org, .text, .data, or .bss) the segment number
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must be given with the .sbase pseudo-instruction.
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The syntax is:
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.br
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.sbase <segment-id> expression
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.br
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with segment-id one of .org, .text, .data, or .bss.
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Example:
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.br
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.sbase .text 0x1000
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.IP registers
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The Intel 8086 has the following 16-bit registers:
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.br
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Four general registers: ax (accumulator), bx (base), cx (count), and dx (data).
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The upper halves and lower halves of these registers are separately
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addressable as ah, bh, ch, dh, and al, bl, cl, dl respectively.
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.br
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Two pointer registers: sp (stack pointer) and bp (base pointer).
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.br
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Two index registers: si (source index) and di (destination index).
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.br
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Four segment registers: cs (code), ds (data), ss (stack), and es (extra).
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.IP "addressing modes"
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.nf
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.ta 8n 16n 24n 32n 40n 48n
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syntax meaning
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expr the value of \fIexpr\fP is immediate data or
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an address offset. There is no special
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notation for immediate data.
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register one of the aforementioned general registers
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or their upper or lower halves, or one of the
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four segment registers.
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(expr) the value of expr is the address of the operand.
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(reg)
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expr (reg) the value of \fIexpr\fP (if present) + the contents of
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\fIreg\fP (which must be a pointer or an index register)
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is the address of the operand.
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(preg) (ireg)
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expr (preg) (ireg)
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the value of \fIexpr\fP (if present) + the contents of
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\fIpreg\fP (which must be a pointer register) + the
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contents of \fIireg\fP (which must be an index register)
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is the address of the operand.
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The next addressing mode is only allowed with the instructions
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"callf" or "jmpf".
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expr : expr the value of the first \fIexpr\fP is a segment number,
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the value of the second \fIexpr\fP is an address offset.
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The (absolute) address of the operand is computed
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as described above.
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.fi
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.IP instructions
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Each time an address is computed the assembler decide which segment register
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to use. You can override the assembler's choice by prefixing the instruction
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with one of eseg, cseg, sseg, or dseg; these prefixes indicate that the
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assembler should choose es, cs, ss, or ds instead.
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.br
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Example:
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.ti +8
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dseg movs
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.SH "SEE ALSO"
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uni_ass(6),
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ack(1),
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.br
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MCS-86 assembly language reference manual, 1978, Intel Corporation
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.SH EXAMPLE
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.nf
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.ta 8n 16n 24n 32n 40n 48n
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An example of Intel 8086 assembly language:
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_panic:
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push bp
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mov bp,sp
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.data
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_35:
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.word 24944
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.word 26990
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.word 14947
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.word 32
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.text
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call _disable
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mov ax,_35
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push ax
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call _str
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pop si
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push 4(bp)
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call _str
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pop si
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call _nlcr
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call _exit
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mov sp,bp
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pop bp
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ret
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.extern _nopanic
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_nopanic:
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push bp
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mov bp,sp
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.data
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_38:
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.word 28526
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.word 24944
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.word 26990
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.word 14947
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.word 32
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.text
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mov ax,_38
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push ax
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call _str
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pop si
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push 4(bp)
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call _str
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pop si
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push 6(bp)
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call _octal
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pop si
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mov sp,bp
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pop bp
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ret
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.fi
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