calculated incorrectly because of overflow errors. Replace it with an extended RELOPPC relocation which understands addis/ori pairs; add an la pseudoop to the assembler which generates these and the appropriate relocation. Make good. --HG-- branch : dtrg-experimental-powerpc-branch
		
			
				
	
	
		
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			C
		
	
	
	
	
	
			
		
		
	
	
			22 lines
		
	
	
	
		
			254 B
		
	
	
	
		
			C
		
	
	
	
	
	
#
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! $Source$
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! $State$
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! $Revision$
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! Declare segments (the order is important).
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.sect .text
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.sect .rom
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.sect .data
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.sect .bss
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#define IFFALSE 4
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#define IFTRUE 12
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#define ALWAYS 20
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#define DNZ 16
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#define LT 0
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#define GT 1
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#define EQ 2
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#define OV 3
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