272 lines
5.8 KiB
C
272 lines
5.8 KiB
C
#define RCSID4 "$Header$"
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/*
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* (c) copyright 1987 by the Vrije Universiteit, Amsterdam, The Netherlands.
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* See the copyright notice in the ACK home directory, in the file "Copyright".
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*
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*/
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operation
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:
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USE16
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{ use32 = 0; address_long = 0; operand_long = 0; }
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USE32
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{ use32 = 1; address_long = 1; operand_long = 1; }
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| prefix oper
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{ address_long = use32; operand_long = use32; }
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| prefix1 /* to allow for only prefixes on a line */
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;
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prefix : /* empty */
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| prefix1
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;
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prefix1: prefix PREFIX { emit1($2); }
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prefix ATOGGLE
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{ if ((($2&0200) >> 7) == address_long) {
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if (pass == PASS_3) warning("address size toggle ignored");
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} else {
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emit1($2 & 0177);
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address_long = ! address_long;
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}
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}
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prefix OTOGGLE
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{ if ((($2&0200) >> 7) == operand_long) {
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if (pass == PASS_3) warning("operand size toggle ignored");
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} else {
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emit1($2 & 0177);
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operand_long = ! operand_long;
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}
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}
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;
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oper : NOOP_1
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{ emit1($1);}
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| NOOP_2
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{ emit2($1);}
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| JOP expr
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{ branch($1,$2);}
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| JOP2 expr
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{ ebranch($1,$2);}
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| PUSHOP ea_1
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{ pushop($1);}
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| IOOP absexp
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{ emit1($1);
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fit(ufitb($2));
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emit1((int)$2);
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}
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| IOOP R32
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{ if ($2!=2) serror("register error");
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emit1($1+010);
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}
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| BITTEST ea_ea
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{ bittestop($1);}
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| ADDOP ea_ea
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{ addop($1);}
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| ROLOP ea_ea
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{ rolop($1);}
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| INCOP ea_1
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{ incop($1);}
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| NOTOP ea_1
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{ regsize($1); emit1(0366|($1&1)); ea_1($1&070);}
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| CALLOP ea_1
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{ callop($1&0xFFFF);}
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| CALFOP expr ':' expr
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{ emit1($1>>8);
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adsize_exp($4, 0);
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#ifdef RELOCATION
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newrelo($2.typ, RELO2);
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#endif
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emit2((int)($2.val));
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}
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| CALFOP mem
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{ emit1(0377); ea_2($1&0xFF);}
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| ENTER absexp ',' absexp
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{ fit(fitw($2)); fit(fitb($4));
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emit1($1); emit2((int)$2); emit1((int)$4);
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}
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| LEAOP R32 ',' mem
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{ emit1($1); ea_2($2<<3);}
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| LEAOP2 R32 ',' mem
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{ emit1(0xF); emit1($1); ea_2($2<<3);}
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| ARPLOP mem ',' R32
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{ emit1($1); ea_2($4<<3);}
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| LSHFT ea_1 ',' R32 ',' ea_2
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{ extshft($1, $4);}
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| EXTEND R32 ',' ea_2
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{ emit1(0xF); emit1($1); ea_2($2<<3);}
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| EXTOP R32 ',' ea_2
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{ emit1(0xF); emit1($1); ea_2($2<<3);}
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| EXTOP1 ea_1
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{ emit1(0xF); emit1($1&07); ea_1($1&070);}
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| IMULB ea_1
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{ regsize(0); emit1(0366); ea_1($1&070);}
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| IMUL ea_2
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{ reg_1 = IS_R32 | (address_long ? 0 : 0310);
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imul(0);
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}
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| IMUL R32 ',' ea_2
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{ reg_1 = $2 | IS_R32 | (address_long ? 0 : 0310);
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imul($2|0x10);
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}
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| IMUL R32 ',' ea_ea
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{ imul($2|0x10);}
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| INT absexp
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{ if ($2==3)
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emit1(0314);
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else {
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fit(ufitb($2));
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emit1(0315); emit1((int)$2);
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}
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}
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| RET
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{ emit1($1);}
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| RET expr
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{ emit1($1-1);
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#ifdef RELOCATION
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newrelo($2.typ, RELO2);
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#endif
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emit2((int)($2.val));
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}
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| SETCC ea_2
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{ emit1(0xF); emit1($1); ea_2(0);}
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| XCHG ea_ea
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{ xchg($1);}
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| TEST ea_ea
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{ test($1);}
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| MOV ea_ea
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{ mov($1);}
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| /* What is really needed is just
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MOV R32 ',' RSYSCR
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but this gives a bad yacc conflict
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*/
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MOV ea_1 ',' RSYSCR
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{
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if ($1 != 1 || !(reg_1 & IS_R32))
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serror("syntax error");
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emit1(0xF); emit1(0x20); emit1(0300|($4<<3)|(reg_1&07));}
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| MOV ea_1 ',' RSYSDR
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{
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if ($1 != 1 || !(reg_1 & IS_R32))
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serror("syntax error");
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emit1(0xF); emit1(0x21); emit1(0300|($4<<3)|(reg_1&07));}
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| MOV ea_1 ',' RSYSTR
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{
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if ($1 != 1 || !(reg_1 & IS_R32))
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serror("syntax error");
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emit1(0xF); emit1(0x24); emit1(0300|($4<<3)|(reg_1&07));}
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| MOV RSYSCR ',' R32
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{
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if ($1 != 1) serror("syntax error");
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emit1(0xF); emit1(0x22); emit1(0300|($2<<3)|$4);}
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| MOV RSYSDR ',' R32
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{
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if ($1 != 1) serror("syntax error");
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emit1(0xF); emit1(0x23); emit1(0300|($2<<3)|$4);}
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| MOV RSYSTR ',' R32
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{
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if ($1 != 1) serror("syntax error");
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emit1(0xF); emit1(0x26); emit1(0300|($2<<3)|$4);}
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/* Intel 80[23]87 coprocessor instructions */
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| FNOOP
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{ emit1($1); emit1($1>>8);}
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| FMEM mem
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{ emit1($1); ea_2(($1>>8)&070);}
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| FMEM_AX R32
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{ if ($2 != 0) {
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serror("illegal register");
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}
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emit1(FESC|7); emit1(7<<5);
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}
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| FST_I st_i
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{ emit1($1); emit1(($1>>8)|$2); }
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| FST_I ST
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{ emit1($1); emit1($1>>8); }
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| FST_ST ST ',' st_i
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{ emit1($1); emit1(($1>>8)|$4); }
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| FST_ST2 ST ',' st_i
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{ emit1($1); emit1(($1>>8)|$4); }
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| FST_ST st_i ',' ST
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{ emit1($1|4); emit1((($1>>8)|$2)); }
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| FST_ST2 st_i ',' ST
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{ emit1($1|4); emit1((($1>>8)|$2)^010); }
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;
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st_i : ST '(' absexp ')'
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{ if (!fit3($3)) {
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serror("illegal index in FP stack");
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}
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$$ = $3;
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}
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;
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;
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mem : '(' expr ')'
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{ if (address_long) reg_2 = 05;
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else reg_2 = 06;
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mod_2 = 0;
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rm_2 = 05;
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exp_2 = $2;
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RELOMOVE(rel_2, relonami);
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}
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| bases
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{ exp_2.val = 0; exp_2.typ = S_ABS; indexed();}
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| expr bases
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{ exp_2 = $1; indexed();
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RELOMOVE(rel_2, relonami);
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}
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;
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bases : '(' R32 ')'
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{ if (address_long) reg_2 = $2;
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else reg_2 = sr_m[$2];
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sib_2 = 0; rm_2 = 0;
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}
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| '(' R32 ')' '(' R32 scale ')'
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{ if (address_long) reg_2 = $2;
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else reg_2 = dr_m[$2][$5];
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rm_2 = 04;
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sib_2 |= regindex_ind[$2][$5];
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}
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| '(' R32 '*' absexp ')'
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{ if ($4 == 1) {
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reg_2 = $2; sib_2 = 0; rm_2 = 0;
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}
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else {
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rm_2 = 04;
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sib_2 = checkscale($4) | regindex_ind[05][$2];
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reg_2 = 015;
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}
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}
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;
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scale : /* empty */
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{ sib_2 = 0;}
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| '*' absexp
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{ sib_2 = checkscale($2);}
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;
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ea_2 : mem
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| R8
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{ reg_2 = ($1 | IS_R8) | (address_long ? 0 : 0300);
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rm_2 = 0;
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}
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| R32
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{ reg_2 = ($1 | IS_R32) | (address_long ? 0 : 0310);
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rm_2 = 0;
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}
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| RSEG
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{ reg_2 = ($1 | IS_RSEG) | (address_long ? 0 : 020);
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rm_2 = 0;
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}
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| expr
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{ reg_2 = IS_EXPR | (address_long ? 0 : 040);
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exp_2 = $1; rm_2 = 0;
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RELOMOVE(rel_2, relonami);
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}
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;
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ea_1 : ea_2
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{ op_1 = op_2;
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RELOMOVE(rel_1, rel_2);
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}
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;
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ea_ea : ea_1 ',' ea_2
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;
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