118 lines
4.1 KiB
Groff
118 lines
4.1 KiB
Groff
.\" $Id$
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.TH I386_AS 6 "$Revision$"
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.ad
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.SH NAME
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i386_as \- assembler for Intel 80386
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.SH SYNOPSIS
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~em/lib.bin/i386/as [options] argument ...
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.SH DESCRIPTION
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This assembler is made with the general framework
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described in \fIuni_ass\fP(6). It is an assembler generating relocatable
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object code in \fIack.out\fP(5) format.
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.SH SYNTAX
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.IP segments
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An address on the Intel 80386 consists of two pieces:
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a segment number and an offset.
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Usually, the segment number resides in a segment register, and
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assembly language addresses only give the offset, with the exception of
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the address of an inter-segment jump or call (see \fIaddressing modes\fP
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below).
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.IP registers
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The Intel 80386 has the following 32-bit registers:
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.br
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Four general registers: eax (accumulator), ebx (base), ecx (count), and edx (data).
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The low- and high order bytes of the low order words of these registers
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are separately addressable as ah, bh, ch, dh, and al, bl, cl, dl respectively.
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.br
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Two pointer registers: esp (stack pointer) and ebp (base pointer).
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.br
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Two index registers: esi (source index) and edi (destination index).
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.br
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Six segment registers: cs (code), ds (data), ss (stack), es (extra),
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fs (extra), and gs (extra).
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.IP "addressing modes"
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.nf
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.ta 8n 16n 24n 32n 40n 48n
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syntax meaning
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expr the value of \fIexpr\fP is immediate data or
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an address offset. There is no special
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notation for immediate data.
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register one of the aforementioned general registers
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or their upper or lower halves, or one of the
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four segment registers.
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(expr) the value of expr is the address of the operand.
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(reg)
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expr (reg) the value of \fIexpr\fP (if present) + the contents of
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\fIreg\fP (which must be a pointer or an index register)
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is the address of the operand.
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(reg1) (reg2)
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expr (reg1) (reg2)
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the value of \fIexpr\fP (if present) + the contents of
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\fIreg1\fP + the
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contents of \fIreg2\fP is the address of the operand.
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(reg1) (reg2 * scale)
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expr (reg1) (reg2 * scale)
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the value of \fIexpr\fP (if present) + the contents of
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\fIreg1\fP + the
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contents of \fIreg2\fP multiplied by \fIscale\fP,
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is the address of the operand.
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\fIscale\fP can be either 1, 2, 4, or 8.
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This mode is only allowed for 32-bit addressing.
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The next addressing mode is only allowed with the instructions
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"callf" or "jmpf".
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expr : expr the value of the first \fIexpr\fP is a segment number,
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the value of the second \fIexpr\fP is an address offset.
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The following two addressing modes are only allowed with Intel 80[23]87 floating
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point processor instructions:
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st
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st(num) addresses the floating point processor stack. \fInum\fP
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must be between 0 and 7. st is the same as st(0).
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.fi
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.IP prefixes
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Each time an address is computed the processor decides which segment register
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to use. You can override the processor's choice by prefixing the instruction
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with one of eseg, cseg, sseg, dseg, fseg, or gseg; these prefixes indicate that the
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processor should choose es, cs, ss, ds, fs, or gs instead.
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.br
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Example:
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.ti +8
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dseg movs
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.IP ""
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There is also an address size toggle, which switches between 32-bit and
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16-bit address generation: a16 or a32. Normally, the assembler generates
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32-bit addresses; both of these toggles make it generate 16-bit addresses
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for the next instruction, and also generate code to set the processor
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temporarily in 16-bit address mode.
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.IP ""
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There is also an operand size toggle, which switches between 32-bit and
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16-bit operands: o16 or o32. Normally, the assembler generates
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32-bit operands; both of these toggles make it generate 16-bit operands
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for the next instruction, and also generate code to set the processor
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temporarily in 16-bit operand mode.
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.IP ""
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Prefixes only affect the next instruction.
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.IP ""
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There are also the .use32 and .use16 assembler directives, which do not
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generate code, but change the assemblers default for operand and address sizes.
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Obviously, .use16 gives 16-bit modes, .use32 gives 32-bit modes.
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This is useful for assembling real mode 80386 code, or pure 16-bit
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modules (that do not have the D-bit set in the segment descriptor).
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These assembler directives stay in effect until there is another one.
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.SH "SEE ALSO"
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uni_ass(6),
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ack(1),
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ack.out(5),
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.br
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80386 Programmer's Reference Manual, 1986, Intel Corporation
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