178 lines
4.1 KiB
Text
178 lines
4.1 KiB
Text
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/* 68000 desciptor table for ACK target optimizer */
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MAXOP 2;
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%%;
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/* useful addressing modes-> */
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CONST {VAL[0] == '#' }; /* constant */
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NUM {is_number(VAL) };
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A,B {no_side_effects(VAL) };
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D {VAL[0] != '#' && !is_areg(VAL) }; /* not an addr. reg */
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X,Y {TRUE };
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DREG,DREG2 {is_dreg(VAL) }; /* data register */
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DSREG {is_dsreg(VAL) }; /* data register */
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AREG {is_areg(VAL) }; /* addressregister */
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LAB,L1,L2 {VAL[0] == 'I' }; /* label */
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BITNO {TRUE };
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%%;
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/* optimization patterns-> */
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/* rewriting rules */
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tst X -> tst.w X ;
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cmp X,Y -> cmp.w X,Y ;
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/* special instructions */
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move.w #0,D -> clr.w D ;
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move.l #0,D -> clr.l D ;
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move.l #0,AREG -> sub.l AREG,AREG ;
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/* tst-elimination */
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add.l #2,sp : tst.w X {no_part("sp",X)} -> move.w X,(sp)+ ;
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add.l #4,sp : tst.l D {no_part("sp",D)} -> move.l D,(sp)+ ;
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add.l #2,sp : move.w X,-(sp) -> move.w X,(sp) ;
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add.l #4,sp : move.l X,-(sp) -> move.l X,(sp) ;
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move.w A,X : tst.w A -> move.w A,X ;
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move.w X,A : tst.w A -> move.w X,A ;
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move.l A,D : tst.l A {no_part(D,A)} -> move.l A,D ;
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move.l X,D : tst.l D -> move.l X,D ;
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move.l A,AREG : tst.l A
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{no_part(AREG,A)} -> tst.l A: move.l A,AREG ;
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move.l X,AREG : move.l AREG,DREG :
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tst.l DREG : beq LAB -> move.l X,DREG :
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move.l DREG,AREG: beq LAB ;
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move.l X,AREG : move.l AREG,DREG :
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tst.l DREG : bne LAB -> move.l X,DREG :
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move.l DREG,AREG: bne LAB ;
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/* redundant move */
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move.w DREG,DREG2 : move.w DREG2,DREG -> move.w DREG,DREG2 ;
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/* register subsumption */
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move.w DREG,A : ANY A,X
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{reg_subs_allowed(ANY) &&
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!is_dreg(A) } -> move.w DREG,A : ANY DREG,X ;
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/* change "cmp" into "add" or "sub" (possibly "addq" or "subq") */
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cmp.w #-NUM,DSREG : beq LAB -> add.w #NUM,DSREG : beq LAB ;
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cmp.l #-NUM,DSREG : beq LAB -> add.l #NUM,DSREG : beq LAB ;
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cmp.w #-NUM,DSREG : bne LAB -> add.w #NUM,DSREG : bne LAB ;
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cmp.l #-NUM,DSREG : bne LAB -> add.l #NUM,DSREG : bne LAB ;
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cmp.w #NUM,DSREG : beq LAB -> sub.w #NUM,DSREG : beq LAB ;
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cmp.l #NUM,DSREG : beq LAB -> sub.l #NUM,DSREG : beq LAB ;
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cmp.w #NUM,DSREG : bne LAB -> sub.w #NUM,DSREG : bne LAB ;
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cmp.l #NUM,DSREG : bne LAB -> sub.l #NUM,DSREG : bne LAB ;
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/* addq and subq */
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lea -1(AREG),AREG -> sub.l #1,AREG ;
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add.w #-NUM,X -> sub.w #NUM,X ;
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add.l #-NUM,X -> sub.l #NUM,X ;
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sub.w #-NUM,X -> add.w #NUM,X ;
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sub.l #-NUM,X -> add.l #NUM,X ;
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/* bit-test instruction */
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move.b X,DSREG : and.w #NUM,DSREG :
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tst.w DSREG : beq LAB
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{ bitno(NUM,BITNO)} -> btst #BITNO,X ;
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/* skip over jump */
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beq L1 : bra L2: labdef L1 -> bne L2 : labdef L1 ;
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bge L1 : bra L2: labdef L1 -> blt L2 : labdef L1 ;
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bgt L1 : bra L2: labdef L1 -> ble L2 : labdef L1 ;
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blt L1 : bra L2: labdef L1 -> bge L2 : labdef L1 ;
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ble L1 : bra L2: labdef L1 -> bgt L2 : labdef L1 ;
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bne L1 : bra L2: labdef L1 -> beq L2 : labdef L1 ;
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%%;
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/* auxiliary routines: */
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int no_side_effects(s)
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register char *s;
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{
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for(;;) {
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switch(*s++) {
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case '\0': return TRUE;
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case '-': if (*s == '(') return FALSE; break;
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case ')': if (*s == '+') return FALSE; break;
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}
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}
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/* NOTREACHED */
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}
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int is_dreg(s)
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register char *s;
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{
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return *s++ == 'd' && *s >= '0' && *s++ <= '7' && *s == '\0';
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}
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int is_dsreg(s)
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register char *s;
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{
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return *s++ == 'd' && *s >= '0' && *s++ <= '2' && *s == '\0';
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}
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int is_areg(s)
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register char *s;
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{
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return *s++ == 'a' && *s >= '0' && *s++ <= '6' && *s == '\0';
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}
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int no_part(part,s)
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char *part,*s;
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{
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char *tmp1,*tmp2;
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while (*s != '\0') {
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if (*s == *part) {
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for (tmp1=part,tmp2=s;; tmp1++,tmp2++) {
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if (*tmp1== '\0') return FALSE;
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if (*tmp1 != *tmp2) break;
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}
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}
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s++;
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}
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return TRUE;
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}
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/* see if register subsumption is allowed for instruction Opc */
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int reg_subs_allowed(opc)
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char *opc;
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{
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return strcmp(opc,"cmp") != 0 && strcmp(opc,"lea") != 0;
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}
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int is_number(s)
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register char *s;
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{
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while (*s != '\0') {
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if (*s < '0' || *s++ > '9') return FALSE;
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}
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return TRUE;
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}
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int bitno(s,no)
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char *s,*no;
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{
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int n,i;
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n = atoi(s);
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if (n < 1 || n > 128) return FALSE;
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for (i = 0; i < 8 ; i++) {
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if (n == 1) {
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sprintf(no,"%d",i);
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return TRUE;
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}
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n >>= 1;
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}
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return FALSE;
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}
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